Papers by Author: Sandro Solmi

Abstract: Comparative studies of gate oxides on a N+ pre-implanted area (Ninterface ~1x1019cm-3) and on a virgin Si face 4H-SiC material (Ninterface ~1x1016cm-3) have been undertaken by means of Capacitance-Voltage (C-V) characteristics, performed at different temperatures and frequencies, and Thermal Dielectric Relaxation Current technique. In the non implanted samples, the stretch out of the C-V curves get larger as the temperature is lowered to 150K, while for lower temperatures the C-V characteristics become steeper and some discontinuities occur. These discontinuities are specific for the non-implanted sample and are associated with charging of the fast near interface states (NIToxfast) via a tunneling from the shallow interface states (Dit). The tunneling from the shallow Dit to NIToxfast supress the a.c. response of Dit, which is recovered only after most of the NIToxfast are charged with electrons.

Abstract: The effect of nitrogen (N) introduced by ion implantation at the SiO2/4H-SiC interface on the capacitance of the MOS capacitors is investigated. The Thermal Dielectric Relaxation Current (TDRC) technique and Capacitance-Voltage (C-V) measurements performed at different temperatures and probe frequencies on an N implanted sample and on a virgin sample were employed for this purpose. There are three types of defects located at or near the interface, Dit, NIToxfast and NIToxslow that can be distinguished. Only Dit and NIToxfast respond to the a.c. small, high frequency signal at temperatures above 150K. The separation of Dit from the NIToxfast states have enabled us to study the influence of the excess of interfacial Nitrogen on each of the mentioned defects. It has been found that the N-implantation process fully suppresses the formation of NIToxfast and partially NIToxslow and Dit. Theoretical C-V characteristics were computed, based on the defect distributions determined by TDRC, and compared with the experimental ones showing a close agreement.

Abstract: In this paper the electrical and structural characteristics of n-MOSFETs fabricated on 4H SiC with a process based on nitrogen (N) implantation in the channel region before the growth of the gate oxide are reported for low (5x1018 cm-3) and high (6x1019 cm-3) N concentration at the SiO2/SiC interface. The electron mobility and the free carrier concentration in the MOSFET channel were evaluated by Hall effect measurement. The MOSFETs with the higher N concentration had the best electrical characteristics in terms of threshold voltage and field effect mobility, in spite of a lowering of the electron mobility in the channel. The latter is a negative drawback of the fabrication process that probably can be ascribed to an incomplete recovery of the implantation damage or to a high density of interstitial N atoms present in the channel region. In fact, the MOSFETs with the superior electrical performances were fabricated with the higher N+ dose and the shorter thermal oxidation time. However, no evidence of extended defects, clusters or nano-particles in SiC at the interface with the gate oxide was found in every SiC MOSFETs devices observed by electron transmission microscopy

Abstract: The electrical characteristics of MOSFETs fabricated on 4H-SiC with a process based on N implantation in the channel region before the growth of the gate oxide are reported as a function of the N concentration at the SiO2/SiC interface up to 6  1019 cm-3. The field effect mobility improves with increasing N concentration. At room temperature values change from 4 cm2/Vs for the not implanted sample up to 42 cm2/Vs for the sample with the highest N concentration. Furthermore, the field effect mobility increases with temperature and presents values above 60 cm2/Vs at 200 °C. The MOSFETs with the better electrical characteristics (higher mobility, lower threshold voltage, lower subthreshold swing) were fabricated by a low thermal budget oxidation process, thank to the use of a high N implantation dose able to produce an amorphous SiC surface layer. A strong correlation among the increasing of the N concentration at the SiO2/SiC interface, the reduction of the interface state density located near the conduction band and the improvement of the MOSFETs performance was obtained.

Abstract: Phosphorous implanted n+/p diodes have been included in the masks for manufacturing n-MOSFET devices and processed in the same way of source/drain regions. The diode junctions were made by a P+ implantation at 300°C and a post implantation annealing at 1300°C. The diode emitter area was protected by 0.6 m thick CVD oxide during the processing of the MOSFET gate oxide. Three gate oxide processes were taken into account: two of them include a N implantation before a wet oxidation, while the third one was a standard oxidation. Considering the effect on the n+/p diodes, the main difference among the processes were the wet thermal oxidation time that ranged between 180 and 480 min at a temperature of 1100°C. The diode current-voltage characteristics show similar forward but different reverse curves in the temperature range of 25-290°C. Differences in reverse bias voltage as a function of the measurement temperature have been analyzed and are related to the different gate oxidation time. A correlation between the shortest oxidation time and the lower leakage current is presented.

Abstract: This work is focusing on the effect of a high concentration of nitrogen (N) introduced by ion implantation at the SiO2/4H-SiC interface in MOS capacitors. The N implanted sample (Ninterface ~1x1019cm-3) is compared with a non-implanted one (Ninterface ~1x1016cm-3) by means of the electron interface trap density (Dit). The Dit is determined via High-Low frequency C-V method and Thermal Dielectric Relaxation Current (TDRC) technique. It is shown that the TDRC method, mainly used so far for determination of near interface oxide charges, can be exploited to gain information about the Dit too. The determined value of Dit in the N-implanted sample is nearly one order of magnitude lower than that in the sample without N implantation. Good agreement between the TDRC results and those obtained from High-Low frequency C-V measurements is obtained. Furthermore, the TDRC method shows a high accuracy and resolution of Dit evaluation in the region close to the majority carrier band edge and gives information about the traps located into the oxide.

Abstract: We report investigations on the fabrication and electrical characterization in the range 27°C -290 °C of normally off 4H-SiC circular MOSFET devices manufactured on p-type semiconductor. An high quality SiO2/SiC interface is obtained by nitrogen ion implantation conducted before the thermal oxidation of SiC. Two samples with different nitrogen concentration at the SiO2/SiC interface and one un-implanted have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. With increasing temperature, in all the samples the threshold voltage decreases and the electron channel mobility increases, reaching the maximum value of about 40 cm2/Vs at 290 °C for the sample with the highest N concentration. The observed improvement of the mobility is related to the beneficial effect of the N presence at the SiO2/SiC interface, which leads to the reduction of the interface trap density with energy close to the conduction band. Our results demonstrate that N implantation can effectively be used to improve the electrical performance of surface n-channel 4H-SiC MOSFETs.

Abstract: 4H-SiC p-type MOS capacitors fabricated by wet oxidation of SiC preamorphized by nitrogen ion (N+) implantation have been investigated. The oxidation rate of the SiC layer preamorphized by high-dose N+ was much larger than that of crystalline SiC, allowing us to reduce the fabrication time of SiC MOS devices. We found that the presence of the surface amorphous SiC layer before the oxidation process did not influence the interface state density in MOS capacitors. Moreover, the shift of the flat-band voltage is not correlated to the amount of nitrogen in the oxide. On the contrary the density of interface states near the valence band edge increased according with the high concentration of the implanted N at the oxide–SiC interface, as in the case of dry oxidation reported by Ciobanu et al. The generation of positive charges due to the nitrogen embedded inside the oxide layer was smaller compared with dry oxidation. We discuss the difference between wet and dry oxidation for MOS capacitors fabricated with N+ implantation.

Abstract: Aiming to minimize the interface state density, we fabricated MOS capacitors on n-type 4H-SiC by using wet oxidation of nitrogen implanted layers. We investigated a wide range of implantation dose, including a high dose able to amorphise a surface SiC layer with the intent to reduce the oxidation time. The oxide quality and the SiO2-SiC interface properties were characterized by capacitance-voltage measurements of the MOS capacitors. The proposed process, in which nitrogen is ion-implanted on SiC layer before a wet oxidation, is effective to reduce the density of interface states near the conduction band edge if a high concentration of nitrogen is introduced at the SiO2-SiC interface. We found that only the nitrogen implanted at the oxide-SiC interface reduces the interface states and we did not observe the generation of fixed positive charges in the oxide as a consequence of nitrogen implantation. Furthermore, the concentration of the slow traps evaluated from the Slow Trap Profiling technique was low and did not depend on the nitrogen implantation fluence.

Abstract: The surface morphology and the electrical activation of P+ implanted 4H-SiC were investigated with respect to annealing treatments that differ only for the heating rate. P+ implantation was carried out in lightly doped n-type epitaxial layers. The implantation temperature was 300 °C. The computed P profile was 250 nm thick with a concentration of 1×1020 cm-3. Two samples underwent annealing at 1400 °C in argon with different constant ramp up rates equal to 0.05° C/s and 40 °C/s. A third sample underwent an incoherent light Rapid Thermal Annealing (RTA) at 1100 °C in argon before the annealing at 1400 °C with the lower ramp rate. The ramp up of the RTA process is a few hundred degrees per second. Atomic Force Microscopy (AFM) micrographs pointed out that the surface roughness of the samples annealed at 1400 °C increases with increasing heating rate and that the critical temperature for surface roughening is above 1100 °C. Independently on the annealing cycle, Scanning Capacitance Microscopy (SCM) measurements showed that the P profiles are uniform over the implantation thickness and have plateau concentration around 9×1018 cm-3 in all the implanted samples. The fraction of P atoms activated as donors is 13% of the total implanted fluence.