Papers by Author: Sarit Dhar

Abstract: Temperature dependent capacitance-voltage (C-V) and constant capacitance transient spectroscopy (CCDLTS) measurements have been performed to investigate the role of N in improving the transport properties of 4H-SiC MOS transistors. The higher channel mobility in the N pre-implanted transistors is due at least in part to activation of a small fraction of the implanted N near the SiO₂/SiC interface as donors in SiC during oxidation, thus reducing the effects of interface trapping. In addition, the absence of oxidation-induced near-interface defects, which were observed in NO-annealed capacitors, may contribute to the improved mobility in N pre-implanted transistors.

Abstract: Hall measurements on NO annealed 4H-SiC MOS gated Hall bars are reported in the temperature range 77 K- 423 K. The results indicate higher carrier concentration and lower trapping at increased temperatures, with a clear strong inversion regime at all temperatures. In stark contrast to Si, the Hall mobility increases with temperature for 77 K-373K, above which the mobility decreases slightly. The maximum experimental mobility was found to be ~50 cm² V^-1 s^-1 which is only about 10% of the 4H-SiC bulk mobility indicating that while NO annealing drastically improves trapping, it does not improve the mobility significantly. Supporting modeling results strongly suggest the presence of a disordered SiC channel region.

Abstract: We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 6.7 mm x 6.7 mm 4H-SiC N-IGBT with an active area of 0.16 cm2 showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. A 4H-SiC P-IGBT exhibited a record high blocking voltage of 15 kV, while showing a differential specific on-resistance of 24 mΩ-cm2. A comparison between P- and N- IGBTs in 4H-SiC is provided in this paper.

Abstract: We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.

Abstract: 4H-SiC MOSFETs with an epitaxial channel and NO postoxidation annealing have Si-like dependencies of noise on gate voltage. Such dependencies indicate that the density of the negatively charged oxide traps responsible for 1/f noise, N_tv, does not depend on the position of the Fermi level. The N_tv was found to be ~ 2×10¹⁹ cm^-3eV^-1. This value is considerably smaller than previously measured for transistors with ion implanted channels.

Abstract: We present physics based models for the occupation of interface traps and the mobility of the transition layer found in 4H-SiC MOSFETs and extract values for the same using combined numerical simulation and experimental characterization. The Si-C-O transition layer found in 4H-SiC MOS devices is electrically modeled as having a doping dependent mobility that is different from the regular bulk 4H-SiC bulk mobility. Compared to the high intrinsic bulk mobility of 4H-SiC, the transition layer intrinsic mobility was extracted to be approximately 165cm2/Vs. The occurrence of the excessive high density of interface traps near the conduction band edge led us to develop a new model for the occupation of traps lying inside the conduction band itself. Due to the conduction band trap densities being comparable to the conduction band electron states, a non-zero probability exists for their occupation, which causes the occupied trap densities to be very high in strong inversion. Detailed numerical simulations and corroboration with experiment have been performed to calibrate the models and extract physical parameter values.

Abstract: In this paper, we review the performance, reliability, and robustness of the current 4H-SiC power DMOSFETs. Due to advances in device and materials technology, high power, large area 4H-SiC power DMOSFETs (1200 V, 67 A and 3000 V, 30 A) can be fabricated with reasonable yields. The availability of large area devices has enabled the demonstration of the first MW class, all SiC power modules. Evaluations of 1200 V 4H-SiC DMOSFETs showed that the devices offer avalanche power exceeding those of commercially available silicon power MOSFETs, and have the sufficient short circuit robustness required in most motor drive applications. A recent TDDB study showed that the gate oxides in 4H-SiC MOSFETs have good reliability, with a 100-year lifetime at 375oC if Eox is limited to 3.9 MV/cm. Future work on MOS reliability should be focused on Vth shifts, instead of catastrophic failures of gate oxides.

Abstract: The electrical properties of the SiC/SiO2 interface resulting from oxidation of the n-type 6H-SiC polytype were studied by hi-lo CV, temperature dependent CV and constant capacitance deep level transient spectroscopy (CCDLTS) techniques. Several trap species differing in energy and capture cross section were identified. A trap distribution at 0.5 eV below the 6H-SiC conduction band energy and a shallower density of states in both the 6H and 4H polytyes are passivated by post-oxidation NO annealing. However, other ultra-shallow and deeper defect distributions remain after nitridation. The latter may originate from semiconductor traps.

Abstract: In this paper, we present the effects of MOS channel processing on the threshold voltage and the MOS field effect mobility of 4H-SiC MOSFETs. By increasing the p-well doping concentration by two orders of magnitude, the threshold voltage could be shifted positive from 0V to 5 V when a thermal oxide layer with NO post oxidation anneal was used as the gate dielectric layer. However, a severe degradation of MOS field effect mobility, decreasing from 37 cm2/Vs to 5 cm2/Vs, was also observed. Using a different processing technique, which uses a deposited oxide layer with an NO anneal, a threshold voltage of 7.5 V and a MOS field effect mobility of 15 cm2/Vs could be achieved. A 10 kV, 1 A power DMOSFET was demonstrated with this technique. A DMOSFET turn-off voltage of 5.25 V was measured at room temperature, which shifted to 3.0 V at 250oC, providing acceptable noise margins throughout the operating temperature range.

Abstract: We report on the effect of nitridation on the negative and positive charge buildup in SiC gate oxides during carrier injection. We observe that the incorporation of nitrogen at the SiO2/SiC interface can enhance the reliability of the interface by suppressing the generation of interface states upon electron injection but that it can also degrade the oxide by creating additional hole traps. We relate these phenomena to the passivation of atomic-level defects by nitrogen.