Papers by Author: Tsutomu Yatsuo

Abstract: We investigate a cascode configuration of a normally-on SiC-Buried Gate Static Induction Transistor (SiC-BGSIT) and Si-MOSFET as an alternative switching device of the SiC-MOSFET. It is shown that the transconductance of our cascode device is much higher than that of commercial SiC-MOSFETs while the switching speed is much faster than that of normally-off SiC-BGSITs. The origin of the fast switching speed in this cascode configuration is discussed in terms of a simulated reverse transfer capacitance.

Abstract: Super-junction (SJ) devices have been developed to improve the trade-off relationship between the blocking voltage (V_BD) and specific on-resistance in unipolar power devices. This SJ structure effect is expected in SiC unipolar devices. Multi-epitaxial growth is a known fabrication method for SJ structures where epitaxial growth and ion implantation are repeated alternately until a certain drift-layer thickness is achieved. In this study, we fabricated two types of test elemental groups with an SJ structure to evaluate the breakdown voltage (V_BD) and specific resistivity of the drift layer (R_drift). Experimental results show that V_BD exceeded the theoretical limit of the 4H-SiC by 300V, and R_drift agreed well with the estimated value from the device simulation. The beneficial effects of the SJ structure in the SiC material on V_BD and R_drift were confirmed for the first time.

Abstract: 3 kV normally-off SiC-buried gate static induction transistors (SiC-BGSITs) were fabricated by using an innovative fabrication process that was used by us previously to fabricate 0.7–1.2 kV SiC-BGSITs. The fabricated device shows the lowest specific on-resistance of 9.16 mΩ·cm², compared to all other devices of the same class. The threshold voltage of this device was 1.4 V at room temperature and was maintained at values more than 1 V with normally-off characteristics at 200 °C. The device can block drain voltage of 3 kV with a leakage current density of 6.9 mA/cm².

Abstract: We have tried to fabricate a super junction (SJ) structure in SiC semiconductors by the trench-filling technique. After the deep trench formation by dry etching, epitaxial layer is grown over the trench surface. Doping profile of the embedded p-type epitaxial region between the trenches is evaluated by a scanning spreading resistance microscopy (SSRM). The SSRM result reveals that the doping profile is not uniform and there exists a low concentration region along the trench side-wall. Based on the SSRM result, two-dimensional device simulations are performed using pn-type test structures with the non-uniform SJ drift layer. The simulation result shows that blocking voltage of the test structure can be optimized and becomes comparable to that of the ideal one by adjusting the concentration design of the embedded layer to balance the total charge in SJ structure.

Abstract: We investigated the short-circuit capabilities of 1.2 kV normally-off SiC buried gate static induction transistors (SiC-BGSITs). The maximum short-circuit energy was found to be 35.6 J/cm2, which is twice that of normally-on SiC-BGSITs and 3.3–5.6 times higher than that of the Si-IGBTs. The maximum short-circuit time was 590 μs. It is concluded that these high short-circuit capabilities result from saturation characteristics of the normally-off SiC-BGSITs.

Abstract: In this work, we succeeded in developing high performance normally-off SiC buried gate static induction transistors (SiC-BGSITs). To achieve the normally-off characteristics, design parameters around the channel region were optimized and process conditions were improved to realize these parameters. The off-state characteristic of the SiC-BGSIT showed an avalanche breakdown voltage of VBR=980 V at a gate voltage of VG=0 V. Furthermore, the leakage current at VD=950 V is lower than 0.5 μA. These results indicate that the BGSIT has a good normally-off characteristic. At VG=2.5 V, an on-resistance of 28.0 mΩ corresponding to the specific on-resistance of 1.89 mΩ•cm2 was obtained and the current rating was calculated as 33 A at a power density of 200 W/cm2 in the on-state characteristic.

Abstract: We investigated the 4H-SiC C-face MOS interface properties around valence-band, and fabricated 4H-SiC C-face p-channel MOSFETs for the first time. For C-face p-channel MOSFETs, relatively low-temperature wet-gate-oxidation was preferable. Post-deposition-annealing for contact metal was found to degrade the C-face MOS interface around valence-band. Low-temperature (800°C) PDA in hydrogen including ambient was effective to some extent in order to suppress the degradation owing annealing. We obtained C-face p-channel MOSFET with normal FET operation by utilizing 900°C wet-gate-oxidation and 800°C PDA in He-H2 forming gas ambient.

Abstract: We fabricated 4H-silicon carbide (SiC) Complementary Metal-Oxide-Semiconductor (CMOS) devices with wet gate oxidation processing. The channel properties of n-channel MOS Field-Effect-Transistor (NMOS) were controlled by buried channel (BC) structure. The electrical properties of CMOS devices depended on the doping concentration of the BC-layer (Nbc) for NMOS. The SiC CMOS inverters with high Nbc indicated fast operation at the delay time (Td) of 4.8 ns for supply voltage of 15 V. To our knowledge, Td obtained in this study is the smallest among the reported values for SiC CMOS inverters.

Abstract: In this study, we evaluated the radiation hardness of SiC Buried Gate Static Induction Transistors (SiC-BGSITs) and Si-based switching devices up to the absorbed dose of 10 MGy(SiO2). The on-voltage Von of Si-IGBT degraded excessively at the early stage of the irradiation (>~0.1 MGy(SiO2)) due to the bulk damage produced by Compton electrons like the gain degradation in Si bipolar transistors. The threshold voltage Vth of Si-MOSFET was very sensitive against the radiation due to the competing mechanism between the generation of the hole traps in the gate SiO2 and the SiO2/Si interface states. Moreover, the breakdown voltage VBR and leak current Ileak of MOSFET degraded significantly against the absorbed dose. While, the electrical properties of SiC-BGSIT was very stable even after the irradiation of 10 MGy(SiO2).

Abstract: It is known that a Schottky barrier height (b) of metal/C-face 4H-SiC Schottky barrier diode (SBD) differ from b of metal/Si-face 4H-SiC SBD. Furthermore, b of metal/4H-SiC SBD varies with annealing temperature. We fabricate 0.231mm2 SBD with Ti/SiC interface using Si-face and C-face 4H-SiC. These SBDs are annealed at several temperatures after a formation of the Ti/SiC interface. As a result, b of Ti/C-face 4H-SiC interface annealed at 400 oC is nearly equal to b of Ti/Si-face 4H-SiC interface annealed at 500 oC and the n-values of these SBDs are nearly equal to the ideal value (unity). Using that annealing condition, we fabricated 25mm2 junction barrier Schottky (JBS) diodes with Ti/SiC interface on Si-face and C-face 4H-SiC epitaxial substrate. b of Si-face and C-face JBS diodes are 1.26eV and 1.24eV, respectively. The leakage currents for both Si-face and C-face JBS diodes are less than 1mA/cm2. The current of 100A is obtained at the forward bias voltage of 1.95V and 2.16V for the Si-face JBS and the C-face JBS.