Papers by Author: Ze Hong Zhang

Abstract: A method was developed in our laboratory to grow low basal plane dislocation (BPD) density and BPD-free SiC epilayers. The key approach is to subject the SiC substrates to defect preferential etching, followed by conventional epitaxial growth. It was found that the creation of BPD etch pits on the substrates can greatly enhance the conversion of BPDs to threading edge dislocations (TEDs) during epitaxy, and thus low BPD density and BPD-free SiC epilayers are obtained. The reason why BPD etch pits can promote the above conversion is discussed. The SiC epilayer growth by this method is very promising in overcoming forward voltage drop degradation of SiC PiN diodes.

Abstract: Dislocations were tracked from 4H-SiC epilayer to the substrate by a new method based on combination of molten KOH etching and Reactive Ion Etching. It was found that basal plane dislocations (BPDs) with dislocation lines parallel (or approximately parallel) to the off-cut direction might propagate as BPDs into the epilayer, while those with dislocation lines forming large angles (>10º) with the off-cut direction will get converted to threading edge dislocations (TEDs). A model is proposed to explain the observations.

Abstract: The nucleation sites of stacking faults (SFs) during forward current stress operation of 4H-SiC PiN diodes were investigated by the electron beam induced current (EBIC) mode of scanning electron microscopy (SEM), and the primary SF nucleation sites were found to be basal plane dislocations (BPDs). Damage created on the diode surface also acts as SF nucleation sites. By using a novel BPD-free SiC epilayer, and avoiding surface damage, PiN diodes were fabricated which did not exhibit SF formation under current stressing at 200A/cm2 for 3 hours.

Abstract: Thick epilayers up to 60 µm have been grown on ) 0 2 11 ( face SiC substrates at a growth rate of 15 µm/hr by chemical vapor deposition (CVD). The epilayer surface is extremely smooth with a RMS roughness of 0.6 nm for a 20µm×20µm area. Threading screw and edge dislocations parallel to the c-axis are present in the ) 0 2 11 ( substrate; however, they do not propagate into the epilayer. The I-V characteristics of the Schottky diodes on this face were studied. Basal plane (0001) dislocations with a density of ~105 cm-2 were found in the ) 0 2 11 ( epilayers by molten KOH etching and electron beam induced current (EBIC) mode of the scanning electron microscope (SEM).