Papers by Keyword: Conductance Method

Abstract: Interface properties of 4H-SiC N-MOS and P-MOS capacitors with two different NO annealing conditions are characterized by the conductance method. With the enhancement of nitrogen passivation, the density of interface states is reduced as expected. Fast interface states (response frequencies >1 MHz) are observed for both N-MOS and P-MOS capacitors with weak NO passivation. After strong NO passivation, the fast states are passivated to the interface states with lower response frequency in N-MOS and significantly suppressed in P-MOS. It indicates that the nitridation may passivate the defects by shifting them from shallow level to deep level.

Abstract: The electrical characteristics of the SiC metal-oxide-semiconductor field effect transistor (MOSFET) have been limited by large amount of states at the SiO₂/SiC interface. In this study, the accuracy of the energy level of the interface states extracted by hypothetical high frequency extreme, which is conventionally used, is experimentally examined. Conductance measurements at low temperature between 65 K and 100 K reveal that the extracted energy distribution of the interface states at nitrided SiO₂/SiC interface close to the conduction band edge depends on the measurement temperature. It is demonstrated that conductance method at 65K enables us more accurate evaluation of the interface states at the SiO₂/SiC interface and found that the interface states density (D_it) of nitride SiO₂/SiC interface is over 10¹³ cm^-2eV^-1 at energy level of 0.1 eV below the conduction band edge.

Abstract: NO annealed Lateral (11-20) MOSFETs were fabricated and mobility limiting mechanisms were investigated by MOS-gated Hall measurements, impedance analysis of MOS capacitor and so on. We have clarified that about 1×10¹² cm^-2 of inversion electrons are trapped at the interface and mobility is largely limited by Coulombic scattering. We attribute that the Coulombic scattering is caused by electrons trapped at interface states and positive fixed charges, which might be due to donor-like states.

Abstract: MOS capacitors have been fabricated on (0001), (11-20) and (000-1) oriented 4H-SiC under different post-oxidation anneal (POA) conditions. 100 MHz conductance measurement shows the generation of very fast donor-type interface traps after NO anneal for both Si-face (0001) and a-face (11-20), but not on C-face (000-1). Fast traps were not observed in POCl₃ annealed samples for any orientation. Smallest D_it (at 0.2 eV below conduction band edge) was obtained on Si-face using POCl₃ anneal (1.4x10¹¹ cm^-2 eV^-1), on a-face using NO anneal (2.5x10¹¹ cm^-2 eV^-1) and on C-face using POCl₃ anneal (4.5x10¹² cm^-2 eV^-1).

Abstract: The effect of phosphorus (P) on the electrical properties of the 4H-SiC / SiO₂ interface was investigated. Phosphorus was introduced by surface-near ion implantation with varying ion energy and dose prior to thermal oxidation. Secondary ion mass spectrometry revealed that only part of the implanted P followed the oxidation front to the interface. A negative flatband shift due to residual P in the oxide was found from C-V measurements. Conductance method measurements revealed a significant reduction of density of interface traps D_it with energy E_C - E_it > 0.3 V for P⁺-implanted samples with [P]_interface = 1.5 10¹⁸ cm^-3 in the SiC layer at the interface.

Abstract: Two electrical measurement techniques are frequently employed for the characteri- zation of traps at the SiO2/SiC interface: the thermal dielectric relaxation current (TDRC) and the conductance method (CM). When plotting Dit as a function of the energy position Eit in the bandgap both techniques reveal comparable results for deep interface traps (EC􀀀Eit > 0:3 eV). For shallower traps, CM always shows a strong increase of Dit which originates from near interface traps (NIT). TDRC provides a contradictory result, namely a slight decrease of Dit. In this paper, we show that the position of NITs in the oxide close to the interface is responsible for the invisibility of these traps in TDRC spectra. We further show that NITs become detectable by the TDRC method by using a discharging voltage Vdis close to the accumulation regime. However, due to the Shockley-Ramo-Theorem the contribution of NITs to the Dit in TDRC spectra is strongly suppressed and can be increased by using thin oxides.

Abstract: In n-type 4H-SiC, over-oxidation of an implanted surface-near, Gaussian nitrogen-profile results in MOS capacitors, which possess a distinctly reduced density of interface states Dit and an undesirable large negative flatband voltage UFB. Their values are determined by the implantation parameters and the thickness of the oxide layer. The negative flatband voltage can strongly be compensated in the case that a Gaussian aluminum-profile is co-implanted prior to the oxidation. Depending on the conditions of the Al implantation, UFB can be controlled within a wide range. Secondary ion mass spectrometry analyses reveal that the implanted N and Al atoms are mobile in the oxide layer during the oxidation process and are partly accumulated at the SiC/SiO2 interface.