Papers by Keyword: Density of Interface States

Abstract: This paper presents process integration of atomic layer deposition (ALD) SiO₂ as gate dielectric in the 1.7 kV SiC trench UMOSFET. This integration provides a solution for embedding complementary metal oxide semiconductor (CMOS) circuits into the UMOSFET power device, enabling the realization of smart power management integrated circuit (IC) functions in the future. 4H-SiC power MOSFETs have gained increased attention in medium to high power applications recently due to their wide bandgap, high breakdown electric field, and excellent thermal conductivity. The electric vehicle (EV) is one example of an application where the Tesla Model 3 utilizes SiC 650V VDMOSFETs as driving components in its inverter design. Trench MOSFETs are key to achieving these requirements to further scale down power devices while decreasing the specific on-state resistance (R_on,sp). This is challenging with thermal gate oxide on SiC trench MOSFETs due to the anisotropic thermal oxide growth rate on the sidewalls and the bottom of trench or mesa region. Therefore, we propose a novel fabrication process by integrating ALD SiO₂ gate oxide into trench UMOSFET. The R_on,sp of the fabricated device can be reduced to 2.3mΩ-cm², accompanied by a very low density of interface states (D_it) of approximately 5.36x10¹⁰ eV^-1cm^-2. Another feature of this ALD SiO₂ solution for gate oxide is the monolithic integration of the CMOS circuit with the UMOSFET, enabling the realization of smart power IC management.

Abstract: We demonstrate our new local deep level spectroscopy system improved for more accurate analysis of trap states at SiO₂/4H-SiC interfaces. Full waveforms of the local capacitance transient with the amplitude of attofarads and the time scale of microseconds were obtained and quantitatively analyzed. The local energy distribution of interface state density in the energy range of E_C − E_it = 0.31–0.38 eV was obtained. Two-dimensional mapping of the interface states showed inhomogeneous contrasts with the lateral spatial scale of several hundreds of nanometers, suggesting that the physical origin of the trap states at SiO₂/SiC interfaces is likely to be microscopically clustered.

Abstract: In this study, electrical properties of MOS capacitors with varying oxide thicknesses have been investigated. The oxide growth was performed at 1050 °C without any further post-oxidation annealing steps resulting in oxide thicknesses between 2 nm and 32 nm. Capacitance-Voltage measurements revealed a decreasing density of interface defects for increasing oxide thickness suggesting a deterioration of the interface at the initial stage of the growth.

Abstract: Key steps in the fabrication of high-efficiency a-Si:H/c-Si heterojunction solar cells are the controlled pyramid texturing of the c-Si substrates to minimize reflection losses and the subsequent passivation by deposition of a high-quality a-Si:H layer to reduce recombination losses. This contribution reviews our recent results on the optimization of the wet-chemical texturing of crystalline Si wafers for the preparation of heterojunction solar cells with respect to low reflection losses, low recombination losses and long minority carrier lifetimes. It is demonstrated, that by joint optimization of both saw damage etch and texture etch the optical and electronic properties of the resulting pyramid morphology can be controlled. Effective surface passivation and thus long minority charge carrier lifetimes are achieved by deposition of intrinsic amorphous Si ((i) a-Si:H) layers. It is shown, that optimized (i) a-Si:H deposition parameters for planar Si (111) wafers can be transferred to a-Si:H layer deposition on random pyramid textured Si (100) wafers. Statistical analysis of the pyramid size distribution revealed that a low fraction of small pyramids leads to longer minority charge carrier lifetimes and, thus, a higher V_oc potential for solar cells.

Abstract: A simple and practical method of characterizing traps at SiC/SiO₂ interfaces close to the bottom of the conduction band by using the split C−V and Hall measurements is proposed. This technique was applied to the characterization of traps at a wet-oxidized SiC/SiO₂ interface on C-face and those at an oxynitrided SiC/SiO₂ interface on Si-face. It was shown that the density of traps near the conduction band of the oxynitrided SiC/SiO₂ interface was more than 10 times larger than that of the wet-oxidized SiC/SiO₂ interface.

Abstract: Conventional MOSFETs and Hall-bar MOSFETs are fabricated side by side by over-oxidation of N-implanted or N-/Al-coimplanted 4H-SiC layers. It is demonstrated that the N-/Al-coimplanted MOSFETs possess a positive threshold voltage at room temperature and reach high values of the channel mobility. The effective electron mobility and Hall mobility in Hall-bar MOSFETs are 31 cm2/Vs and 150 cm2/Vs, respectively, indicating a high density of interface traps in spite of the excellent high mobility values.

Abstract: The purpose of this work is to compare the density of shallow interface states (Dit) at the interface of SiO2/SiC MOS capacitors as deducted by the conductance spectroscopy (CS) and thermally dielectric relaxation current (TDRC) techniques. Both capacitors of 4H- and 6H-SiC (n-type) are investigated, and both ordinary dry oxidation and an improved industrial procedure have been employed. The two techniques are found to give rather good agreement for interface states located ≥0.3 eV below the conduction band edge (Ec) while for more shallow states vastly different distributions of Dit are obtained. Different reasons for these contradictory results are discussed, such as strong temperature and energy dependence of the capture cross section of the shallow interface states.

Abstract: Available data on Schottky barrier heights on silicon and carbon rich faces of 4H-SiC have been carefully analyzed to investigate the mechanism of barrier formation on these surfaces. As in case of 3C and 6H-SiC, the barrier heights depend strongly upon method of surface preparation with a considerable scatter in the barrier height for a given metal-semiconductor system. However, for each metal the barrier height depends on the metal work function and strong pinning of the Fermi level has not been observed. The slopes of the linear relation between the barrier heights and metal work functions varies over a wide range from 0.2 to about 0.75 indicating that the density of interface states depends strongly on the method of surface preparation. By a careful examination of the data on barrier heights we could identify a set of nearly ideal interfaces in which the barrier heights vary linearly with metal work function approaching almost to the Schottky limit. The density of interface states for these interfaces is estimated to lie between 4.671012 to 2.631012 states/ cm2 eV on the silicon rich surface and about three times higher on the carbon rich faces. We also observed that on these ideal interfaces the density of interface states was almost independent of metal indicating that the metal induced gap states (MIGS) play no role in determining the barrier heights in metal-4H-SiC Schottky barriers.

Abstract: In n-type 4H-SiC, over-oxidation of an implanted surface-near, Gaussian nitrogen-profile results in MOS capacitors, which possess a distinctly reduced density of interface states Dit and an undesirable large negative flatband voltage UFB. Their values are determined by the implantation parameters and the thickness of the oxide layer. The negative flatband voltage can strongly be compensated in the case that a Gaussian aluminum-profile is co-implanted prior to the oxidation. Depending on the conditions of the Al implantation, UFB can be controlled within a wide range. Secondary ion mass spectrometry analyses reveal that the implanted N and Al atoms are mobile in the oxide layer during the oxidation process and are partly accumulated at the SiC/SiO2 interface.

Abstract: Temperature-dependent Hall effect investigations in the channel of lateral 3C-SiC LDDMOSFETs with nitrogen(N)-implanted source/drain regions are conducted. The free electron concentration and the electron Hall mobility are independently determined. A maximum electron Hall mobility of 75 cm2/Vs is observed. The gate oxide withstands electric field strengths up to 5 MV/cm. A high density of interface states of a few 1013 cm-2eV-1 close to the 3C-SiC conduction band edge still lowers the performance of the MOS device.