Papers by Keyword: Etch Rate

Abstract: For horizontally stacked nanowires or-sheets to compete with finFET, the development of a robust inner spacer module is essential. These inner spacers are required to reduce the parasitic capacitance due to the overlap between the source/drain and gate regions. Here we propose an inner spacer integration scheme for Si gate-all-around (GAA) taking advantage of the selective oxidation and oxide removal of SiGe versus Si. Compared to thermal oxide, we found a very high SiGe-oxide etch rate in aqueous HF solutions. When using an NH₃/NF₃ remote plasma, a reduction in etch rate was found for SiGe-oxide versus thermal oxide. We show Si_0.75Ge_0.25-oxide meets inner spacer requirements for leakage current and electrical breakdown field and finally demonstrate the proposed inner spacer integration scheme using a fin-shaped SiGe/Si multilayer topological-test-structure.

Abstract: We investigated selective etching of SiC in molten KOH + NaOH + Na₂O₂ mixtures in application to defect analysis. Etch rate was measured as a function of etchant composition, temperature and other process variables. Optimal etching conditions were established for reliable differentiation between TSDs, TEDs, BPDs and stacking faults (SF).

Abstract: High temperature (>1000 °C) chemical etching using molten KCl or molten KCl+KOH as the etchant has been carried out to remove the mechanical-polishing (MP) induced damage layer from 4H-SiC surface. Atomic force microscopy observations have shown that line-shaped surface scratches that have appeared on the as-MPed surface could be completely removed by KCl-only etching or by KCl+KOH etching (KCl:KOH=99:1 in weight) at ~1100 °C. Between the two recipes, KCl+KOH etching has shown a higher etch rate (6~7 times) and is able to remove ~9 μm and ~36 μm-thick damage layer from the Si (0001) and the C(000-1) surface, respectively. Besides, KCl+KOH etching seems to have formed a Si (0001) surface covered with atomic steps while KCl-only etched surface is featured with nanometer-scale pores.

Abstract: Dry etching of Pt/Ti film was carried out using Cl₂/Ar plasmas in an inductively coupled plasma (ICP) reactor. The influence of the various process parameters, such as RIE power, ICP power and Cl₂/Ar gas mixing ratio, on the etch rate and selectivity of photoresist to Pt/Ti film were investigated systematically and optimized. It was revealed that the etch rate and the selectivity strongly depended on the key process parameters. The etch rate was found to increase dramatically with increasing of RIE power and ICP power. But by changing the ratio of Cl₂ to the total gas, the maximum etch rate could be obtained at the proper ratio of 20%. The results also indicated too low or too high RIE power and the Cl₂ ratio was detrimental to the selectivity. The optimized parameters of Pt/Ti dry etching for high etch rate and low selectivity of photoresist to Pt/Ti were obtained to be pressure: 10mT, RF power: 250W, ICP power: 0W, Cl₂: 8sccm (standard cubic centimeters per minute), Ar: 32sccm.

Abstract: In the process of deep etching of silicon, the metal film or the oxide film served as silicon protective layer needed to be etched before using plasma etching technology. In order to solve the etch rates variance of different aperture sizes and different pitchs periodic patterns, by controlling the water bath temperature and etching time, the etch rates of different aperture sizes and different pitchs periodic patterns at 50 degree centigrade had been developed. Also we contrasted the etching results at different bath temperatures and got the controllable and suitable wet etching bath temperature 50 degree centigrade. At last, the paper further explores the effects of feature size and the wet etching bath temperature on etch rate.

Abstract: In the semiconductor wafer cleaning, ammonium hydroxide based APM (ammonium peroxide mixture) has been widely used to remove particles and organic contaminants [. However as the film thickness and line width of semiconductor structure scales down rapidly, the material losses by etching reaction of alkaline chemicals can cause serious problem in yield loss due to electric failure. The presence of H₂O₂ could enhance the material loss on silicon wafer. Very dilute alkaline chemicals might be of interest since it could minimize any possible ionic contamination or chemical residues from chemicals as long as we control the surface roughness and particle removal efficiency. Also the characterization of these very dilute alkaline chemicals will be very useful for particle removal in gas dissolved DI water.

Abstract: Compound semiconductors based on group III and V elements of the periodic system have high charge carrier mobility and are, therefore, candidates for channel material in future CMOS devices [1]. In order to design wet chemical solutions that lead to appropriate surface pre-conditioning and allow for nanoscale processing and minimal substrate loss, a thorough understanding of the interactions between the substrate and the chemical solutions is needed and the basic etching mechanisms needs to be resolved. The focus of this research is on InP in acidic solutions. ESH aspects are also considered.

Abstract: Since silicon will ultimately face physical limitations, germanium and III-V materials, such as Ga, GaAs, InGaAs, are being extensively investigated for their high electron and hole mobility advantages. Prior to implementing germanium or III-V materials, it is believed that SiGe with high Ge concentration will be applied for channel materials in pMOS devices with high-k and metal gates in order to simultaneously adjust the work function and to increase the hole mobility. However, introduction of new channel materials leads to new challenges and substantial changes in the FEOL process flow.

Abstract: In semiconductor processing, test wafers are used as particle monitors, film thickness monitors for deposition and oxide growth measurements, dry/wet etch rate monitors, CMP monitors, as well as characterizing new and existing equipment and processes. Depending on fab size and capacity, monthly test wafer usage can be tens of thousands or more. Due to the ever increasing demand for silicon between the IC and solar markets and the high cost of 300mm wafers, chip manufacturers are increasing their efforts to reduce overall spending on silicon - currently by far the largest non equipment related cost [1]. One approach taken by many chip makers is the concept of extending the usable life of test wafers by re-using them as many times as possible through a reclaim process.

Abstract: The Si transistor has dominated the semiconductor industry for decades. However, to fulfill the demands of Moore’s law, the Si transistor has been pushed to its physical limits. Introducing new materials with higher intrinsic carrier mobility is one way to solve this problem. Ge, GaAs and InGaAs are known for their high mobilities and are therefore suitable candidates for replacing Si as a channel material. However, introduction of new materials raises new issues. For Si processing, several steps such as cleaning, etching and stripping are based on wet treatments. The knowledge of etch rates of the semiconductor material is of great importance. In this paper, etch rates of Ge, GaAs and InGaAs in several chemical solutions are studied. A comparison of the etch rates is made between the materials.