Papers by Keyword: Logic Gate

Abstract: In this paper a method for synthesizing Reduced Multi-Valued Logic Networks (RMVLNs) using NZMDD is presented. MVL functions represented as large MVLNs are reduced by RMVLN. The detailed working of NZMDD method is presented elaborately in this paper. It is observed that reduced average Product Term (PT) is achieved in MVL synthesis using NZMDD. Experimental analysis is carried out by examining randomly generated 49998 non-sequential benchmark circuits. An improvement average PT reduction of 12.486% is noted in comparison to evolutionary ACO-MVL algorithm.

Abstract: The fluorescence of N-methyl-1-naphthymethylamine (NA) was reversible modulated by acid and base based on switching photoinduced electron transfer (PET) process, which constituted a reversible on –off switch. However, addition of a calix [4] arene-spiropyran (Calix-2sp) derivative, which has absorption from 200 nm to 400 nm, caused that the fluorescence of protonated NA (NAH) was quenched and it could not be return to its initial high value by means of addition of acid again. Thus, the system made up of an INHIBIT logic gate.

Abstract: The main goal of the paper is to provide a drawn up methodic for proposal of technical system optimization in terms of maximizing its reliability at given sum of financial costs or minimizing finance to achieve set reliability. The system reliability, respectively causal relationships between system failures and its elements faults are analyzed and illustrated by using special method called fault tree analysis (FTA) and technical system is represented by fault trees. Subsequently, the genetic algorithms are appropriately applied on the constructed diagram. The part of this paper is the proposal and description of individual steps of genetic algorithm in order to optimize fault tree analysis.

Abstract: versatile gate is a multipurpose device, which can be transformed into any types of gates, amplifier, differentiator, and integrator. It has control inputs which guides transformation of this device. This implies that any chip made of this device can change hardware structure just by using software program. This enables hardware upgrading without buying new chips. This reduces electronic wasteland, which proves that it is very ergonomic and environmental friendly.

Abstract: A difference-frequency mixer based on exclusive-or gates with a filter at the output, which processes a variable frequency input signal and a reference input signal (produced by measurement system) to develop an output signal representative of the frequency difference between the two input signals, was studied in theory and simulation experiments. Digital difference-frequency mixers of this kind can be used in the output signal measurement of resonator-based sensors for high resolution and short measure time.

Abstract: Chaos computing is a new circuit design scheme of using chaos computing units to achieve reconfigurable logic gates. The computing unit can function as different kinds of logic gates by changing external parameters. In this paper, the possibilities of expanding the function of a chaotic NOR gate proposed in the literature is studied. The numerical model for the circuit design was built by constructing differential equations fit for Matlab integration mechanism. Besides, numerical model for integrator saturation was built to make results of numerical simulation conform to that of circuit simulation. Analysis of the impact of integrator saturation was done. With the analysis and by changing the control voltage, NAND function was expanded for the original chaotic logic gate that was only able to function as a NOR gate. By adding the function control signal to the input end and setting the voltage of it to different levels, the computing unit becomes a real time reconfigurable one.

Abstract: Normally-off 4H-SiC MOSFETs are used to build NMOS logic gates intended for high temperature operation. The logic gates are characterized between 25°C and 500°C. Stable gate operation for more than 200h at 400°C in air is demonstrated. The excellent MOS reliability is quantified using I-V curves to dielectric breakdown and constant voltage stress to breakdown at 400°C. Although the effective tunneling barrier height B for electrons lowers to 2eV at 400°C, the extrapolated lifetime from constant voltage stress to breakdown measurements is longer than 105h at 400°C for typical logic gate operating field strength of 2MV/cm.

Abstract: The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 °C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 °C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 °C to +500 °C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

Abstract: This paper updates the long-term 500 °C electrical testing results from 6H-SiC junction field effect transistors (JFETs) and small integrated circuits that were introduced at ICSCRM-2007. Two packaged JFETs have now been operated in excess of 7000 hours at 500 °C with less than 10% degradation in linear I-V characteristics. Several simple digital and analog demonstration integrated circuits successfully operated for 2000-6500 hours at 500 °C before failure.