Authors: Kosuke Uchida, Toru Hiyoshi, Yu Saito, Hiroshi Egusa, Tatsushi Kaneda, Hirotaka Oomori, Takashi Tsuno
Abstract: 1200 V / 200 A V-groove trench MOSFET optimized to achieve low power loss, high oxide reliability under a drain bias condition and high avalanche ruggedness is shown in this paper. We revealed a relationship between the lifetime under a high temperature reverse bias condition and the oxide electric field. In accordance with the results of the test, the 1200 V / 200 A trench MOSFET showed an improvement in the tradeoff between the on-resistance and oxide electric field with the presence of current spreading layers. In order to obtain low on-resistance and high avalanche ruggedness at the same time, buried guard ring structures, which made the blocking voltage of the edge termination area higher than that of the active area, was developed. The fabricated MOSFETs demonstrated a low specific on-resistance of 3.1 mΩ cm2. A predicted lifetime of 200 years under a high temperature drain bias condition of 1200 V was achieved by the optimized design. A short circuit withstand time of 6 μs and a high avalanche energy of 7.8 J/cm2 were shown.
776
Authors: Aiko Ichimura, Yasuhiro Ebihara, Shuhei Mitani, Masato Noborio, Yuichi Takeuchi, Shoji Mizuno, Toshimasa Yamamoto, Kazuhiro Tsuruta
Abstract: The authors have developed 4H-SiC trench MOSFETs with orthogonal Deep-P structures (ODSs) to improve the trade-off between the on-resistance and the gate oxide field. The conditions of photolithography to realize a miniaturized Deep-P pattern have been optimized. The fabricated MOSFETs with ODS have demonstrated a low on-resistance of 2 mΩcm2 and a high breakdown voltage of 1.8 kV.
707
Authors: Dethard Peters, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Daniel Kueck, Romain Esteve
Abstract: A detailed analysis of the typical static and dynamic performance of the new developed Infineon 1200V CoolSiCTM MOSFET is shown which is designed for an on-resistance of 45 mΩ. In order to be compatible to various standard gate drivers the gate voltage range is designed for-5 V in off-state and +15 V in on-state. Long term gate oxide life time tests reveal that the extrinsic failure evolution follows the linear E-model which allows a confident prediction of the failure rate within the life time of the device of 0.2 ppm in 20 years under specified use condition.
489
Authors: Yu Zhu Li, Peter Alexandrov, Jian Hui Zhang, Larry X. Li, Jian Hui Zhao
Abstract: SiC JFET, compared with SiC MOSFET, is attractive for high power, high temperature
applications because it is free of gate oxide reliability issues. Trenched-and-Implanted VJFET (TIVJFET)
does not require epi-regrowth and is capable of high current density. In this work
we demonstrate two trenched-and-implanted normally-off 4H-SiC vertical junction field-effect
transistors (TI-VJFET), based on 120μm, 4.9×1014cm-3 and 100μm, 6×1014cm-3 drift layers. The
corresponding devices showed blocking voltage (VB) of 11.1kV and specific on-resistance (RSP_ON)
of 124m7cm2, and VB of 10kV and RSP_ON of 87m7cm2. A record-high value for VB
2/RSP_ON of
1149MW/cm2 was achieved for normally-off SiC FETs.
1187
Authors: Lin Cheng, Janna R. B. Casady, Michael S. Mazzola, V. Bondarenko, Robin L. Kelley, Igor Sankin, J. Neil Merrett, Jeff B. Casady
Abstract: In this work we have demonstrated the operation of 600-V class 4H-SiC vertical-channel
junction field-effect transistors (VJFETs) with 6.6-ns rise time, 7.6-ns fall time, 4.8-ns turn-on and
5.4-ns turn-off delay time at 2.5 A drain current (IDS), which corresponds to a maximum switching
frequency of 41 MHz – the fastest ever reported switching of SiC JFETs to our knowledge. At IDS
of 12 A, a 19.1 MHz maximum switching frequency has been also achieved. Specific on-resistance
(Rsp-on) in the linear region is 2.5 m·cm2 at VGS of 3 V. The drain current density is greater than
1410 A/cm2 at 9 V drain voltage. High-temperature operation of the 4H-SiC VJFETs has also been
investigated at temperatures from 25 °C to 225 °C. Changes in the on-resistance with temperature
are in the range of 0.90~1.33%/°C at zero gate bias and IDS of 50 mA. The threshold voltage
becomes more negative with a negative shift of 0.096~0.105%/°C with increasing temperature.
1183
Authors: Jian Hui Zhang, Jian Wu, Peter Alexandrov, Terry Burke, Kuang Sheng, Jian Hui Zhao
Abstract: This paper reports recent progress in the development of high power 4H-SiC BJTs based
on an improved device design and fabrication scheme. Near theoretical limit high blocking voltage
of VCEO=1,836 V has been achieved for 4H-SiC BJTs based on a drift layer of only 12 μm, doped to
6.7x1015 cm-3. The collector current measured for a single cell BJT with an active area of 0.61 mm2
is up to IC=9.87 A (JC=1618 A/cm2). The collector current is 7.64 A (JC=1252 A/cm2) at VCE=5.9 V
in the saturation region, corresponding to an absolute specific on-resistance (RSP_ON) of 4.7 m9·cm2.
From VCE=2.4 V to VCE= 5.8 V, the BJT has a differential RSP_ON of only 3.9 m9·cm2. The current
gain is about 8.8 at Ic=5.3 A (869 A/cm2). This 4H-SiC BJT shows a V2/RSP_ON of 717 MW/cm2,
which is the highest value reported to date for high-voltage and high-current 4H-SiC BJTs. A verylarge
area 4H-SiC BJT with an active area of 11.3 mm2 is also demonstrated.
1417
Authors: Makoto Mizukami, Osamu Takikawa, Seiji Imai, Kozo Kinoshita, Tetsuo Hatakeyama, Tomokazu Domon, Takashi Shinohe
Abstract: A 4H-SiC 600 V class Deep-Implanted gate Vertical JFET (DI-VJFET) is examined. The DI-VJFET exhibited a specific on-resistance of 13 mΩcm2, drain current of 5 A, and a blocking-voltage of 600 V. In this paper, the very high temperature dependence (R.T.~ 400 oC) of the I-V characteristics is
measured and the dominant factor of the on-resistance and the blocking-voltage is discussed. Moreover, the switching waveform of SiC DI-VJFET with SiC SBD is measured by using a half bridge, double-pulse circuit with inductive load at R.T. and 200 oC. The turn-off time is 300 ns at an inductance of 4 mH and an external gate resistance of 100 Ω.
881