Papers by Keyword: Shallow Trench Isolation

Abstract: Shallow trench isolation via chemical mechanical polishing (CMP-STI) tests of Si wafers using CeO₂ slurry were studied. The impact of CeO₂ slurry's solid concentration on the SiO₂ removal rate and the selectivity ratio The effects of the solid concentration of CeO₂ slurry on the removal rate of SiO₂ and selectivity (SiO₂/Si₃N₄) were investigated. The CeO₂ abrasive was well matched to the XRD standard pattern, confirming that it had a cubic phase and the absence of any impurities. The SEM image showed that CeO₂ primary particles had a spherical-like shape with a size within 30-60 nm. Additionally, the prepared CeO₂ slurry showed a relatively high dispersion level. The wettability degree of the CeO₂ slurry on top of the Si wafer surface was also sufficient. Furthermore, results from polishing tests indicated that both the SiO₂ removal rate and the selectivity increased linearly with a rise in CeO₂ solid concentration.

Abstract: As the DRAM design rule has been smaller, the leaning normally occurred in storage pattern with high aspect ratio also appears in STI (shallow trench isolation) pattern of sub 4Xnm device. IPA (isopropyl alcohol) showing the excellent ability to replace DIW (de-ionized water) is necessary in order to meet the leaning free condition, because the spin drying method cannot satisfy with leaning free condition.

Abstract: The ambient and denuded trench top corner at the step of gate oxidation play an important role to generate defect. Furthermore, dislocation-free flash process is proposed, and its mechanism as well. The impact on dislocation of the other processes is also discussed. And we knew that using of dry oxidation for gate oxide has the characteristic to reduce the dislocation. Consequently, the dislocation free wafer is obtained by changing gate oxide from wet to dry in manufacturing embedded flash.