Papers by Keyword: SiC Device

Abstract: The electronic packaging has developed in the changing trend from soldering to solderless technology bonding to achieve higher performance of devices. Moreover, power electronic devices have searching for an alternative interconnection technology to replace the high temperature solder with high Pb contents, particularly suitable for next-generation wide band-gap (WBG) semiconductors such as SiC or GaN. In this study, our pressureless Ag thin-film die-attach gives an opportunity to produce the mass production by realizing low-temperature process. We demonstrate the pressureless Ag thin-film die-attach with Si and SiC to explain the mechanisms underlying the bonding process. The variation of the substrate material modifies the thermal expansion mismatch between sputtered Ag film and the substrate, and changes the bonding property, in particular die-shear strength. We reveal that the thermal stress generated by heating plays one of key roles to control the pressureless Ag thin-film die-attach process.

Abstract: This paper addresses the design diagnostic study of 4H-SiC based IGBTs using two dimensional numerical computer simulations. Using identical set of physical device parameters (doping, thicknesses), simulated structure was first calibrated with the experimental data. A minority carrier life time in the drift layer of 1.0 1.6 μs and contact resistivity of 0.5 - 1.0 x 10^-4 Ω-cm² produces a close match with the experimental device. A decay in the device transconductance and threshold voltage is observed with increasing temperature. The on-resistance first decays with temperature (i.e., increased in ionization level, and increase in minority carrier life time), stays nearly constant with further increase in the temperature (may be all carriers are now fully ionized and increase in carrier life time is compensated with decrease in the carrier mobility) and finally increases linearly with temperature (> 450 K) due to decrease in the carrier mobility. The design of buffer layer is investigated that shows lower on-state losses with thin high doped buffers. For the design of devices over 15 20 kV, the design of drift layer demands a doping of < 2.0 x 10¹⁴ cm^-3 with epitaxial layer quality giving a carrier life time over 2.0 μs.

Abstract: To solve the problem of the limitation to improve device performance in standard Si integration technologies and to develop radiation-harsh devices, the irradiation effects of Si_1-xC_x source/drain (S/D) n-type metal oxide semiconductor field effect transistors (n-MOSFETs) have been investigated. It is shown that the drain current and the maximum electron mobility of Si_1-xC_x n-MOSFETs decrease by electron irradiation. The reduction of the device performance can be explained by the radiation-induced lattice defects in the devices. However, the electron mobility enhancement effect by adding C remained after an electron irradiation up to 5×10¹⁷ e/cm².

Abstract: N-LDMOS and n-LIGBT structures were manufactured with the same dimensions on a 4H-SiC wafer in order to allow for a direct comparison. The comparison of the devices includes output and transfer characteristics, blocking characteristics, and temperature behavior.

Abstract: This paper addresses and evaluates the temperature dependence performance of silicon carbide (4H-SiC) based insulated gate bipolar transistors (IGBTs) using two dimensional numerical computer aided design tool (i.e., Atlas TCAD from Silvaco). Using identical set of device physical parameters (doping, thicknesses), simulated structure was first caliberated with the experimental data. A minority carrier life time in the drift layer of 1.0 – 1.6 µs and contact resistivity of 0.5 - 1.0 x 10-4 Ω-cm2 produces a close match with the experimental device. A set of n type IGBT structures were then numerically simulated to extract the conduction losses for various blocking voltage classes. An on-resistance first decays with temperature (i.e., increased in ionization level, and increase in minority carrier life time), stays nearly constant with further increase in the temperature (may be all carriers are now fully ionized and increase in carrier life time is compensated with decrease in the carrier mobility) and finally increases linearly with temperature (>450 oC) due to decrease in the carrier mobility. Compared with Si based IGBTs, numerical simulation predicts lower VCEON and RON values for 4H-SiC based IGBTs for higher voltage classes and hence potential for achieving smaller conduction losses for SiC based IGBTs.

Abstract: The new MOSFET-generation with SiC-materials seems well suited for power electronic converters up to 1200 V operating-voltage, and particularly for grid-feeding PhotoVoltaic-inverters, which transfer the DC power of the solar panel to the AC grid. Their high switching speed and low on-resistance RDS(on) allow the use of higher switching frequencies, which could mainly reduce the costs and weight of the converters. This paper shows a comparison between IGBT and SiC DMOSFET devices and first measurements of some 1200 V / 10 A SiC-DMOSFET samples made by CREE®.

Abstract: The performance of SiC MOSFET devices to date is below theoretically expected performance levels. This is widely considered to be attributed to defect at the SiO2/SiC interface that degrade the electrical performance of the device. To analyze the relationship between defect structures near the interface and electrical performances, advanced computer simulations were performed. A slab model using 444 atoms for an amorphous oxide layer on a 4H-SiC (0001) substrate was made by using first-principles molecular dynamic simulation code optimized for the Earth-Simulator. Simulated heating and rapid quenching was performed for the slab model in order to obtain a more realistic structure and electronic geometry of a-SiO2/4H-SiC interface. The heating temperature, the heating time and the speed of rapid quenching were 4000 K, 3.0 ps and -1000 K/ps, respectively. The interatomic distance and the bond angles of SiO2 layers after the calculation are agree well with the most probable values of bulk a-SiO2 layers, and no coordination defects were observed in the neighborhood of SiC substrate.