A Data Drivered Refresh with Multi-Bit Error-Correcting Power Optimize Method for Cache Based eDRAM

Abstract:

Power problem has been one of most restricting the development barriers of processor. With enhancing of computer performance, there must be large cache to hide memory latency. Large cache can be consisted on one chip based eDRAM which has high density. Unfortunately, eDRAM must be refreshed frequently to maintain data, which would increase cache power. The paper aims at refresh problem of eDRAM, and put forwards a data drivered refresh with multi-bit error-correcting power optimize method. The experimental results show that the method which we put forward can greatly reduce the refresh power of eDRAM.

• Periodical: Advanced Engineering Forum (Volumes 6-7)
• Pages: 20-25
• DOI: https://doi.org/10.4028/www.scientific.net/AEF.6-7.20
• Online since: September 2012
• Authors: Yu Feng Guo
• Keywords: eDRAM, Multi-Bit Error-Correcting, Power, Refresh Power

References

[1] R. Matick, S. Schuster. Logic based eDRAM: origins and rationale for use [J]. IBM Journal of Research and Development, 2005, 49(1): 145~165.

DOI: 10.1147/rd.491.0145

[2] Inc Micron Technology. TN-41-01 : Calculating memory system power for DDR3. http: /download. micron. com/pdf/ technotes/ddr3/TN41_01DDR3%20Power. pdf.

[3] M. Ghosh, H. Lee. Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs[C]. the 40th International Symposium on Microarchitecture, (2007).

DOI: 10.1109/micro.2007.13

[4] Mrinmoy Ghosh, Hsien-Hsin S. Lee. Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs[C]. 40th IEEE/ACM International Symposium on Microarchitecture, MICRO 2007, Chicago, IL, United states: Inst. of Elec. and Elec. Eng. Computer Society, 2007: 134~145.

DOI: 10.1109/micro.2007.13

[5] W. Kong. Analysis of retention time distribution of embedded DRAM - A new method to characterize across-chip threshold voltage variation[C]. IEEE International Test Conference (ITC 2008), 2008: 1~7.

DOI: 10.1109/test.2008.4700556

[6] Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, et al. Reducing cache power with low-cost, multi-bit error-correcting codes[C]. 37th International Symposium on Computer Architecture, ISCA 2010, Saint-Malo, France: Institute of Electrical and Electronics Engineers Inc., 2010: 83~93.

DOI: 10.1145/1815961.1815973

[7] R. Venkatesan, S. Herr, E. Rotenberg. Retention aware placement in DRAM (RAPID): Software methods for quasi-non-volatile DRAM[C]. 12th International Symposium on High Performance Computer Architecture (HPCA), 2006: 155~165.

DOI: 10.1109/hpca.2006.1598122

[8] Jonathan Chang, Ming Huang, Jonathan Shoemaker, et al. The 65-nm 16-MB shared on-die L3 cache for the Dual-Core Intel Xeon Processor 7100 Series [J]. IEEE Journal of Solid-State Circuits, 2007, 42(Compendex): 846~852.

DOI: 10.1109/jssc.2007.892185

[9] J. Kim, M. Papaefthymiou. Block-based multiperiod dynamic memory design for low data-retention power[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2003, 11(6): 1006~1018.

DOI: 10.1109/tvlsi.2003.817524

[10] T. Ohsawa, K. Kai, K. Murakami. Optimizing the DRAM refresh count for merged DRAM/Logic LSIs [C]. Proceedings of the 1998 International Symposium on Low Power Electronics and Design (ISLPED), 1998: 82~87.

DOI: 10.1145/280756.280792

[11] P. Emma, W. Reohr, M. Meterelliyoz. Rethinking refresh: Increasing availability and reducing power in DRAM for cache applications [J]. Micro IEEE, 2008, 28(6): 47~56.

DOI: 10.1109/mm.2008.93

[12] Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg. Retention-Aware Placement in DRAM (RAPID): Software methods for quasi-non-volatile DRAM[C]. Twelfth International Symposium on High-Performance Computer Architecture, Austin, TX, United states: Institute of Electrical and Electronics Engineers Computer Society, 2006: 157~167.

DOI: 10.1109/hpca.2006.1598122

[13] Mrinmoy Ghosh, Hsien-Hsin S. Lee. Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs[C]. 40th IEEE/ACM International Symposium on Microarchitecture, MICRO 2007, Chicago, IL, United states: Inst. of Elec. and Elec. Eng. Computer Society, 2007: 134~145.

DOI: 10.1109/micro.2007.13