FPGA Implementation of Rational Symmetric Biorthogonal 11-9 Wavelet Transform

Abstract:

Coefficients of most existing wavelets are irrational, and it costs much hardware resources when implementing on FPGA, which is inefficient especially in embedded system. Some rational wavelets can overcome this deficiency by elaborate design. Motivated by previous works on rational wavelets, we establish a hardware structure for rational 1-D symmetric biorthogonal 11-9 wavelet and implement it on Xilinx FPGA XC3S500E. The experiment reveals that the area in slices of rational 1-D 11-9 wavelet is less than 1/2 of the pipelined 9-7 wavelet when implementing on FPGA.

• Periodical: Applied Mechanics and Materials (Volumes 182-183)
• Pages: 1791-1795
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.182-183.1791
• Online since: June 2012
• Authors: Ming Zhang, Zhuo Ma, Min Xuan Zhang
• Keywords: Biorthogonal, Field-Programmable Gate Array (FPGA), Rational, Symmetric, Wavelet

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