High-Speed and Anti-Interference Parallel Bus Design on Board

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Abstract:

This paper presents a high-speed and anti-interference parallel bus design on board, which takes a series of measures, including source-synchronous technology, the negative feedback technology, low-voltage differential transmission technology, error correction coding and pseudo-random code technology to improve the environment for parallel communication, increase communication speed, decrease error rate .The final test shows the communication speed has achieved 10 Gbps and the error rate has reduced to 10-7.

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515-519

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June 2012

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© 2012 Trans Tech Publications Ltd. All Rights Reserved

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