Clock Skew Scheduling with Optimizing-Potential Prediction

Article Preview

Abstract:

This paper addresses the issue of increasing the efficiency of the clock skew scheduling. The past research focuses on reducing the time complexity of clock skew scheduling algorithm. However, even if an algorithm has time complexity close to linear, the flow iterations still consumes a lot of time. In this paper, a novel clock skew scheduling scheme with the feature of optimization-potential prediction is proposed. With this feature, the algorithm has timing complexity close to linear, and the number of flow iterations is decreased. The experiment results show that the proposed scheme consumes about half time and achieves almost the same optimization strength (13% highest frequency improvement of ARM1136J-FS) compared to the traditional.

You might also be interested in these eBooks

Info:

Periodical:

Pages:

621-625

Citation:

Online since:

September 2012

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2012 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] J. P Fishburn, Clock skew optimization, IEEE Transactions on Computers, vol. 39, pp.945-951, July (1990).

DOI: 10.1109/12.55696

Google Scholar

[2] L. W. Cotten. Circuit implementation of high-speed pipeline systems. In Proceedings of the Fall Joint Computer Conference. pp.489-504. (1965).

Google Scholar

[3] Robert Tarjan. Depth-first search and linear graph algorithms. Switching and Automata Theory, 1971., 12th Annual Symposium on. Pp 114-121.

DOI: 10.1109/swat.1971.10

Google Scholar

[4] Haoxing, R., D.Z. Pan, D.S. Kung, Sensitivity guided net weighting forplacement-driven synthesis. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2005, 24(5): 711~721.

DOI: 10.1109/tcad.2005.846367

Google Scholar

[5] Sherwani, N., Algorithms for VLSI Physical Design Automation, 3rd. 1999, Boston, USA: Kluwer Academic.

Google Scholar

[6] Bazargan, K., Samjung, K., Sarrafzadeh,M. Nostradamus: a floorplanner ofuncertain designs. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 1999, 18(4).

DOI: 10.1109/43.752923

Google Scholar