Stress Analysis under Cu Bump Bonding Process

Abstract:

The copper wire has some advantages in thermal performance, mechanical performance, and low cost, which make it can provide the lowest cost flip-chip(FC) package for low I/O density device. The 2D Cu stud bump finite element model was set up by using ANSYS/LS-DYNA with LOLID162 element to dynamic simulate the Cu stud bump bonding shaping process. The stress distribution in the Cu stud bump and the pad during the bonding process were studied, and the influence of pad thickness on the stress distribution of Si chip was also analyzed. The results shows that under the bonding process the Cu bump height is mainly influenced by the bonding pressure and the top shape of the Cu bump is influenced by ultrasonic energy, the increase of pad thickness results in reducing stress concentration inside the Si chip.

• Periodical: Applied Mechanics and Materials (Volumes 217-219)
• Pages: 2317-2321
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.217-219.2317
• Online since: November 2012
• Authors: Chun Yue Huang, Ying Liang, Song Wu, Tian Ming Li
• Keywords: Bonding Process, Cu Stud Bump, Finite Element Analysis (FEA), Stress Distribution

References

[1] Fuquan Li, Chunqing Wang, ZHNG Xiaodong. Bump fabrication methods for flip chip [J]. Electronics Process Technology. 2003, 24(2):62-66.

[2] Yanhong Wu, Heng Yang, Shiyi Tang. Fabrication of Gold Stud Bumps for Flip Chip [J]. Semiconductor Technology. 2007, 32(11):926-928.

[3] Hui Guo, Daqi Guo. Technology of many gold studs for flip-chip [J]. Electronics & Packaging 2007,7( 6):18-20

[4] Hui Xu, Chunjing Hang, Chunqing Wang, Yanhong Tian. Contrast research on the reliability of gold and copper wire/ball bonding [J].Equipment for Electronic Products Manufacturing. 2006,(5):23-28.

DOI: 10.1109/icept.2005.1564648

[5] Lee Levine. The application of copper stud bump technology in Flip Chip [J]. Application of IC.2006,(08):41-48.