Design and Implementation of a Fractional Frequency Divider for Dual Mode Wireless Receivers

Xiang Ning Fan; Bin Li; Wei Wei Zhu; Lu Yu; Yu Jie Wang

doi:10.4028/www.scientific.net/AMM.229-231.1591

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 229-231Design and Implementation of a Fractional...

Design and Implementation of a Fractional Frequency Divider for Dual Mode Wireless Receivers

Abstract:

In this paper, a fractional frequency divider (FFD) is designed for Phase-Locked-Loop (PLL) based Frequency Synthesizer, which can be used for GPS/Galileo and WCDMA dual-mode receivers. Based on a dual-modulus prescaler (DMP) and a programmable frequency divider (FD), the integer part can cover from 513 to 760. The fractional part is realized by improved MASH1-1-1 Delta-Sigma (Δ-Σ) modulator (DSM). The whole fractional frequency divider is implemented in TSMC 0.18μm CMOS process, occupying a chip area of 0.714mm2. With the voltage supply of 1.8V, the operating frequency range of the fractional frequency divider is 0.5-5.3GHz; and its supply current is about 5.9mA.

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Periodical:

Applied Mechanics and Materials (Volumes 229-231)

Pages:

1591-1594

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.229-231.1591

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Online since:

November 2012

Authors:

Xiang Ning Fan, Bin Li, Wei Wei Zhu, Lu Yu, Yu Jie Wang

Keywords:

Delta-Sigma Modulator, Dual-Mode, Fractional Frequency Divider, Frequency Synthesizer, Phase-Locked-Loop, Programmable Counter

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