[1]
Z. Jing, Q. Qiusong, S. Weifeng and L. Siyang in: Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress, Journal of Semiconductor vol. 31 (2010).
DOI: 10.1088/1674-4926/31/1/014003
Google Scholar
[2]
R. Boylestad and L. Nashelsky: Electronic Devices And Circuit Theory (Prentice Hall, 2002).
Google Scholar
[3]
M. T. Rahimo, N. Y. A. Shammas in: Freewheeling Diode Reverse Recovery Failure Modes in IGBT Applications, IEEE Trans (2001) Vol. 37, p.661.
DOI: 10.1109/28.913734
Google Scholar
[4]
P. H. Aaen, J. Wood, Q. Li and E. Mares in: Thermal Résistance Modeling for the Electrothermal Layout of High-Power RF Transistor. IEEE (2010), p.1672.
DOI: 10.1109/mwsym.2010.5518198
Google Scholar
[5]
N. Agarwala, K. N. Sharma, J. R. Tsai, Adarsh B, G. Sheu and S. M. Yang in : Effect of Finger and Device-Width on Ruggedness of nLDMOS Device under Single-Pulse Unclamped Inductive Switching (UIS) Conditions , ECS Trans (2012) Vol. 44, p.1123.
DOI: 10.1149/1.3694438
Google Scholar
[6]
N. Agarwala, K. N. Sharma, J. R. Tsai, G. Sheu and S. M. Yang in: Optimization of nLDMOS Ruggedness under Unclamped Inductive Switching (UIS) Stress Conditions by Poly-Gate Extension, ECS Trans (2012) Vol. 44 p.127.
DOI: 10.1149/1.3694306
Google Scholar
[7]
T. Sugiyama, S. Yamazaki, S. Nakagaki and M. Ishiko in: A study of correlation between traps and reverse-recovery characteristics of FWDs, IEEE ISPSD (2005). Power Semiconductor Device and ICs, p.243.
DOI: 10.1109/ispsd.2005.1487996
Google Scholar
[8]
K. Nishiwaki, T. Kushida, and A. Kawahashi in: A Fast & Soft Recovery Diodes with Ultra small Qrr (USQ-Diode) Using Local Lifetime Control by He Ion Irradiation. ISPSD (2001) p.235.
DOI: 10.1109/ispsd.2001.934598
Google Scholar
[9]
R. R. Stoltenbury in: Boundary of Power MOSFET, Unclamped Inductive Switching (UIS), and Avalanche Current Capability, IEEE Applied Power Electronics Conferences (1989), p.359.
DOI: 10.1109/apec.1989.36987
Google Scholar
[10]
F. Chimento, S. Musumeci, A. Raciti, S. Sannino, A. Magri, M. Melito, and F. Zara in: Robustness Evaluation of MOSFETs by Equivalent Cell Behavioral Model of the Gate Parasitic Resistance, IEEE IAS (2007), p.350.
DOI: 10.1109/07ias.2007.48
Google Scholar