Development of High-Speed Memory Interface Application Based on FPGA

Abstract:

In order to make a convenient interface to the complexity of the timing of high-speed, high-capacity storage medium applications, a new design has been proposed for the interface device of storage media with FIFO feature based on DDRII SDRAM by this thesis. At first, the principles and implementation of DDRII SDRAM controller are introduced. Then the memory interface module has been designed based on the time-sharing technique of DDRII SDRAM. Finally, the principles of the interface controller module have been deeply analyzed and implemented by functional simulation through the Quartus II software and FPGA hardware verification. Through stimulation and verification, the high-speed memory interface controller module based on DDRII SDRAM implemented the bi-directional data transfer and interaction between DDRII memory and FPGA, which has a certain value of practical application.

• Periodical: Applied Mechanics and Materials (Volumes 236-237)
• Pages: 1004-1009
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.236-237.1004
• Online since: November 2012
• Authors: Xiao Bo Zhou, Rui Jing Li, Qiang Zhao
• Keywords: DDRII SDRAM, Field-Programmable Gate Array (FPGA), FIFO, Ip Core, Time-Sharing Technique

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