Efficient Utilization of FPGA Using LUT-6 Architecture

Razia Zia; Muzaffar Rao; Arshad Aziz; Pervez Akhtar

doi:10.4028/www.scientific.net/AMM.241-244.2548

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 241-244Efficient Utilization of FPGA Using LUT-6...

Efficient Utilization of FPGA Using LUT-6 Architecture

Abstract:

Field Programmable gate array (FPGA) technology is continuously gaining market share and becoming essential part of the today’s modern embedded systems. The most common FPGA architecture consists of an array of logic blocks called Configurable Logic Block (CLB), I/O pads, and routing channels. In general, a logic block (CLB) consists of logical cells called Slices and other dedicated resources. A typical cell consists of LUTs (Look up table). In modern FPGAs, there are 6-input LUTs instead of 4-input LUTs. In this paper we present the use of 6-input LUT architecture for some Boolean functions (Mux8, Mux16, Mux32, Mux64, SOP64, OR40 and AND40).we show our results in terms of LUTs and Slices and these results are much better as compare to previously reported results that based on 4-input LUTs.

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Periodical:

Applied Mechanics and Materials (Volumes 241-244)

Pages:

2548-2554

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.241-244.2548

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Online since:

December 2012

Authors:

Razia Zia, Muzaffar Rao, Arshad Aziz, Pervez Akhtar

Keywords:

Field-Programmable Gate Array (FPGA), LUT-6 Architecture

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