Phase Locked Loop Pulse Signal Frequency Multiplication Circuit Design Based on FPGA

Ying Ying Zhou; Yu Ming Shen

doi:10.4028/www.scientific.net/AMM.241-244.661

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 241-244Phase Locked Loop Pulse Signal Frequency...

Phase Locked Loop Pulse Signal Frequency Multiplication Circuit Design Based on FPGA

Abstract:

Phase locked loop pulse interpolation technique requires for the input pulse signal frequency multiplication processing. With FPGA as the core, by detecting the edge of the input pulse signal the separate frequency factor was generated, then frequency division of the system clock was realized according to the separate frequency factor, thus phase locked loop frequency multiplication processing of the input pulse signal was completed. The simulation results show that this method has the advantages of high precision and short frequency response time, etc.

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Periodical:

Applied Mechanics and Materials (Volumes 241-244)

Pages:

661-664

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.241-244.661

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Online since:

December 2012

Authors:

Ying Ying Zhou, Yu Ming Shen

Keywords:

Circuit Design, Field-Programmable Gate Array (FPGA), Frequency Multiplication, Phase Locked Loop

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References

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