Debugging Tool for TTA-Based Co-Design Environment

Liang Yao; Zhi Song Bie; Can Feng Chen; Xian Jun Jiao; Xin Zhang

doi:10.4028/www.scientific.net/AMM.263-266.1953

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 263-266Debugging Tool for TTA-Based Co-Design Environment

Debugging Tool for TTA-Based Co-Design Environment

Abstract:

The lack of an effective debugging tool has become a serious constraint to the development of TTA and TCE. In this paper we analyze in depth the requirements of debugging a TTA processor and then present a relatively perfect debugging system which can meet the requirements well. Design details of hardware and software are introduced later on. At last some test results and analysis are discussed.

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Periodical:

Applied Mechanics and Materials (Volumes 263-266)

Pages:

1953-1956

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.263-266.1953

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Online since:

December 2012

Authors:

Liang Yao, Zhi Song Bie, Can Feng Chen, Xian Jun Jiao, Xin Zhang

Keywords:

Application Specific Instruction-Set Processor (ASIP), Debugging Requirements, Debugging Tool, Transport Triggered Architecture, TTA-Based Co-Design Environment

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References

[1] H. Corporaal, Microprocessor Architectures: From VLIW to TTA, John Wiley & Sons, Chichester, UK, (1997)

Google Scholar

[2] Tampere Univ. of Tech., "TCE project at TUT." http://tce.cs.tut.fi

Google Scholar

[3] A. Cilio, H.J.M. Schot, J.A.A.J. Janssen, Processor Architecture Definition File Format for a New TTA Design Framework, unpublished

Google Scholar

[4] Perttu Salmela, Implementations of Baseband Functions for Digital Receivers, Ph.D. Thesis, Tampere Univ. Tech., Finland, Aug. (2009)

Google Scholar

[5] Bart Vermeulen, Sandeep Kumar Goel, Design for Debug: Catching Design Errors in Digital Chips, IEEE Design & Test, v.19 n.3, pp.37-45, May (2002)

DOI: 10.1109/mdt.2002.1003792

Google Scholar

[6] P. Jääskeläinen, "Instruction Set Simulator For Transport Triggered Architec-tures," Master's thesis, Tampere Univ. Tech., Tampere, Finland, Sept. (2005)

Google Scholar