Reliability LU Appropriate Designs in an HV nLDMOS

Shen Li Chen; Tzung Shian Wu

doi:10.4028/www.scientific.net/AMM.271-272.1082

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 271-272Reliability LU Appropriate Designs in an HV nLDMOS

Reliability LU Appropriate Designs in an HV nLDMOS

Abstract:

In an nLDMOS, both the drain-side and source-side engineering by adding N_ad and P_ad layers to obtain a weak snapback characteristic are presented in this work. In this paper, we will detailedly discuss the trigger voltage (V_t1) and holding voltage (V_h) distribution of a novel high-voltage (HV) nLDMOS device. It’s a novel method to reduce the V_t1 and to increase the V_h. Therefore, these efforts will be very suitable for the HV applications in power management ICs.

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Periodical:

Applied Mechanics and Materials (Volumes 271-272)

Pages:

1082-1086

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.271-272.1082

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Online since:

December 2012

Authors:

Shen Li Chen, Tzung Shian Wu

Keywords:

Electrostatic Discharge (ESD), High Voltage (HV), Holding Voltage (V_h), Latch-Up (LU), Lateral Diffused MOS (LDMOS), Snapback, Trigger Voltage (V_t1)

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References

[1] V. De Heyn, G Groeseneken, B. Keppens, M. Natarajan, L. Vacaresse and G. Gallopyn: IEEE International Reliability Physics Symposium, Orlando (2001), p.253.

DOI: 10.1109/relphy.2001.922910

Google Scholar

[2] W. Y. Chen, M. D. Ker, Y. J. Huang, Y. N. Jou and G. L. Lin: IEEE Proceedings of Asia Pacific Conference on Circuits and Systems (2008), p.61.

Google Scholar

[3] A. W. Ludikhuize: Proc. of the 6th Internat. Symposium on Power Semiconductor Devices & IC's, Davos, Switzerland (1994), p.249.

Google Scholar

[4] P. Hower, J. Lin, S. Pendharkar, B. Hu, J. Arch, J. Smith and T. Efland: The 17th International Symposium on Power Semiconductor Devices and ICs Proceedings (ISPSD '05), p.327.

DOI: 10.1109/ispsd.2005.1488022

Google Scholar

[5] J. F. Chen, S. Y. Chen, K. S. Tian, K. M. Wu, Y. K. Su, C. M. Liu, and S. L. Hsu: IEEE International Conference Integrated Circuit Design & Technology (2007), p.1.

Google Scholar

[6] W. Y. Chen, M. D. Ker, Y. N. Jou, Y. J. Huang and G. L. Lin: 16th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA 2009), p.41.

Google Scholar

[7] A. Tanaka, Y. Oritsuki, H. Kikuchihara, M. Miyake, H.J. Mattausch, M. Miura-Mattausch, Y. Liu, K. Green: IEEE Transactions on Electron Devices, Vol.58, Issue 7 (2011), p.2072.

DOI: 10.1109/ted.2011.2132135

Google Scholar