A BIST Structure for ADC in Mixed-Signal SOC

Shi Rong Yin; Chao Tao Liu

doi:10.4028/www.scientific.net/AMM.278-280.950

Paper Titles

The Design and Implementation of PLC Monitoring System Based on OPC
p.930

The Design of SO₂ Sensor Node for Monitoring Table Grape Logistics
p.936

The Development and Study of Hoist Hydraulic Braking Safety Online Monitoring System
p.942

The Study and Design of a UDP Flow Measurement System
p.946

A BIST Structure for ADC in Mixed-Signal SOC
p.950

Micro-Current Signal Acquisition of Formaldehyde Detection Based on the MSP430
p.954

Brain Electrical Signal Digital Processing System Design
p.958

A Optimization Algorithm for the Frequency Domain Fault Location
p.962

Constrained Total Least Squares Algorithm Applied to Three-Axis Magnetometer Calibration
p.968

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 278-280A BIST Structure for ADC in Mixed-Signal SOC

A BIST Structure for ADC in Mixed-Signal SOC

Abstract:

A BIST structure for ADC test in Mixed-Signal SOC to characterize both the dynamic and static parameters was presented. A Sigma-Delta modulation based sinewave generator was built on the chip. The frequency, amplitude and phase of the sinusoidal signal can be adjusted through proper selecting generator parameters which are stored in ADC WBR. The response analyzer was built up from the memory and computational resource in the SOC.

You might also be interested in these eBooks

Advances in Mechatronics and Control Engineering

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 278-280)

Pages:

950-953

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.278-280.950

Citation:

Cite this paper

Online since:

January 2013

Authors:

Shi Rong Yin, Chao Tao Liu

Keywords:

ADC Test, BIST, Mixed-Signal SOC

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] Kuen-Jong Lee, Soon-Jyh Chang and Ruei-Shiuan Tzeng, A Sigma-Delta Modulation Based BIST Scheme for A/D Converters, Proceedings of the 12th Asian Test Symposium (ATS'03), pp: 1-4.

DOI: 10.1109/ats.2003.1250796

Google Scholar

[2] M. F. Toner and G. W. Roberts, A Frequency Response, Harmonic Distortion, and Intermodulation Distortion Test for BIST of a Sigma-Delta ADC, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-11: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 43, NO. 8, AUGUST 1996 pp: 608-613.

DOI: 10.1109/82.532008

Google Scholar

[3] Hsin-Wen Ting, Bin-Da Liu, and Soon-Jyh Chang, A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters, Proceedings of the 13th Asian Test Symposium (ATS 2004).

DOI: 10.1109/ats.2004.18

Google Scholar

[4] Vladimir A. Zivkovic, Jan Schat, Frank van der Heyden, and Geert Seuren, Core-Based Testing of Embedded Mixed-Signal Modules in a SoC, IEEE Design & Test of Computers, May/June 2009, pp: 78-86.

DOI: 10.1109/mdt.2009.55

Google Scholar

[5] IEEE Std 1500-2005, IEEE Standard for Embedded Core Test, IEEE, 2005, http: /grouper. ieee. org/groups/1500/index. html.

Google Scholar

[6] IEEE Std 1149. 4-1999, Mixed-Signal Test Bus, IEEE, 1999, http: /grouper. ieee. org/groups/1149/4/index/html.

Google Scholar

[7] Dominique Dallet, José Machado da Silva, Dynamic Characterisation of Analogue-to-Digital Converters, Science Press in China. (2007).

Google Scholar