A Single-Phase Energy-Recovery Register Using Drowsy Cache and MTCMOS Techniques for Leakage Reductions

Abstract:

Article Preview

With rapid technology scaling, the leakage dissipation is becoming a major source in CMOS circuits because of the increasing sub-threshold and gate leakage current in nanometer CMOS processes. This paper presents an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) using MTCMOS power-gating and drowsy cache techniques to reduce both sub-threshold leakage and gate oxide leakage current dissipations. A 32 X 32 single-phase adiabatic register file are verified using HSPICE. BSIM4 model is adopted to reflect leakage currents in nanometer CMOS processes with gate oxide materials. Simulation results show that leakage losses are greatly reduced.

Info:

Periodical:

Edited by:

Honghua Tan

Pages:

1937-1942

DOI:

10.4028/www.scientific.net/AMM.29-32.1937

Citation:

H. Li et al., "A Single-Phase Energy-Recovery Register Using Drowsy Cache and MTCMOS Techniques for Leakage Reductions", Applied Mechanics and Materials, Vols. 29-32, pp. 1937-1942, 2010

Online since:

August 2010

Export:

Price:

$35.00

In order to see related information, you need to Login.

In order to see related information, you need to Login.