IP Core Design for Parameterized (2,1,N) Convolutional Encodes

Abstract:

In this paper, we design and implement general parameterized IP (Intellectual Property) cores of convolutional encoder with SMIC 0.35μm CMOS technology, serial structure and parallel structure respectively. And analyze each of the power dissipation using Synopsys PTPX tool. The result shows the parallel circuit structure saves 14 percent power dissipation compared to that of serial circuit structure, with the same encode radio. Meanwhile, computing speed of parallel structure with 8-bit parallelism is 8 times than that of serial structure under the same clock frequency. Certainly, serial circuit structure has their particular characters such as easily realized and less resource consumption.

• Periodical: Applied Mechanics and Materials (Volumes 336-338)
• Pages: 1463-1468
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.336-338.1463
• Online since: July 2013
• Authors: Mao Qiang Duan, Xiao Li Huang, Zhi Jia Yang
• Keywords: Convolutional Encodes, Parallel Comoputing, Parameterized IP Core

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