Data Transmission Hardware Design of IPv6 Node for Internet of Things

Abstract:

To reduce the resource consumption in traditional software IPv6 Internet protocols based on embedded system, a data transmission hardware scenario of reduced IPv6 protocol with optimized cache structures based on the FPGA is designed using Verilog HDL. This scenario implements the function of the Transport Layer and the Network Layer on FPGA and uses the function of the Data Link Layer and the Physical Layer on the DM9000A chip, which can perform stateless auto-configuration, address resolution, echo response and UDP transmission. To improve the transmission efficiency, a low-resource-consumption and self-managed cache structure is designed to manage the Neighbor Cache, the Prefix Table and the Default Router Table. In the IPv6 network test, the design can configure itself and its data rate exceeds 28Mbps, which can realize real-time video stream, audio stream and other data transmission in Network of Things applications in IPv6 network.

• Periodical: Applied Mechanics and Materials (Volumes 336-338)
• Pages: 2494-2499
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.336-338.2494
• Online since: July 2013
• Authors: Rong Jun Chen*, Kai Xie, Shun Dao Xie, Xiong Yong Zhu, Hong Zhou Tan
• Keywords: Field-Programmable Gate Array (FPGA), Hardware Protocol Stack, IPv6, Network of Things, Node

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