Flat Knitting Machine Design Based on Display Accelerator

Abstract:

In this paper, the application of a FPGA-based large-screen and high-resolution display accelerator technology in full-automatic textile machinery (computerized flat knitting machine) is studied. The design of traditional computerized knitting machine system is difficult to support the display of large screen and high resolution operating interface. Therefore, a displaying accelerator is designed in this paper. It comprises of FPGA, configuration chip, SDRAM and LVDS transmitter chip, is located between the embedded main processor and high resolution TFT LCD screen of computerized flat knitting machine, and implements the modules such as display acceleration logic and SDRAM controller relying on Verilog HDL programming in FPGA. The computerized flat knitting machine, applying displaying acceleration technology, can present its dynamic color interface on an 800 x 600 resolution TFT LCD (10.4") on the condition that real time, reliability and cost can be ensured.

• Periodical: Applied Mechanics and Materials (Volume 340)
• Pages: 8-12
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.340.8
• Online since: July 2013
• Authors: Ji Ye Huang, Ming Yu Gao
• Keywords: Computerized Flat Knitting Machine, Display Acceleration, Field-Programmable Gate Array (FPGA), SDRAM Controller, TFT LCD

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