Effects of Creep Parameters of Lead-Free Solders on Fatigue Reliability of 3D IC Packages with through Silicon Vias

Abstract:

3D IC packaging technologies are emerging as they are able to respond to the demands for smaller form-factor, faster, high density interconnection at cheaper cost. Moreover, for a 3D IC package, through silicon vias (TSVs) provide high wiring density interconnection, thus improve electrical performance due to shorter interconnection from the chip to the substrate. However, TSV technology is still facing severe challenges as the physical design problems due to the existence of the copper vias remain resolved. Apart from thermal expansion mismatch, the problems are due in part to the nonlinear behavior of SAC lead-free solder used in the package as an echo of environmental concerns and RoHS directive. However, there exists a wide range of values of the parameters of the creep model used to describe the nonlinear behavior of SAC. The effects of the variations of these parameters on the thermal reliability of IC packages, particularly the 3D IC package with built-in TSVs considered herein, is of interest. Presented in the paper is a study on assessment of the influence of the creep parameters of SAC solders on the isothermal fatigue reliability of a 3D IC package with built-in TSVs. The results show that as the strain rate is linear proportional to C₁, a larger C₁ tends to enlarge the strain rate hence decrease the fatigue life. However, the relationship between the fatigue life of the specific IC package is not linear. Although the variation of C₂ causes a large variation in the fatigue life, its effect becomes insignificant when a moderate value of C₂ is considered. As a power parameter to the hyperbolic sine function of the creep model, C₃ contributes a 40% variation to the fatigue life. Lastly, the fatigue life increases with C₄ value, and the gain of fatigue life increases as C₄ approaches the upper limit considered herein.

• Periodical: Applied Mechanics and Materials (Volume 378)
• Pages: 617-623
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.378.617
• Online since: August 2013
• Authors: Chieh Kung
• Keywords: 3D IC Package, Creep, Finite Element Method (FEM), Lead-Free Solder, Through Silicon Vias

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