Cooperative Mechanism of Local Memory and Cache in Network Processors

Abstract:

Traditional network processors (NPs) adopt either local memory mechanism or cache mechanism as the hierarchical memory structure. The local memory mechanism usually has small on-chip memory space which is not fit for the various complicated applications. The cache mechanism is better at dealing with the temporary data which need to be read and written frequently. But in deep packet processing, cache miss occurs when reading each segment of packet. We propose a cooperative mechanism of local memory and cache. In which the packet data and temporary data are stored into local memory and cache respectively. The analysis and experimental evaluation shows that the cooperative mechanism can improve the performance of network processors and reduce processing latency with little extra resources cost.

• Periodical: Applied Mechanics and Materials (Volumes 380-384)
• Pages: 1969-1972
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.380-384.1969
• Online since: August 2013
• Authors: Bo Yuan, Jin Dou Fan, Bin Liu
• Keywords: Cache, Hierarchical Memory Structure, Local Memory, Network Processor

References

[1] Abuhmed T, Mohaisen A, Nyang D, A Survey on Deep Packet Inspection for Intrusion Detection Systems. Magazine of Korea Telecommunication Society, vol. 24, No. 11, pp.25-36, November (2007).

[2] Mochalski K, Schulze H, Deep Packet Inspection, White Paper. http: /www. ipoque. com/sites/default/files/mediafiles/documents/white-paper-deep-packet-inspection. pdf.

[3] Intel IXP 2800 and IXP2850 Network Processors. September 2004 http: /int. xscale-freak. com/XSDoc/IXP2xxx/b1_qual_report. pdf.

[4] http: /int. xscale-freak. com/XSDoc/IXP2xxx/b1_qual_report. pdf.

[5] Intel IXP2800 Network Processor Hardware Reference Manual. August 2004, http: /int. xscale-freak. com/XSDoc/IXP2xxx/27888201. pdf.

[6] OCTEON II CN68XX Multi-Core MIPS64 Processors. http: /www. cavium. com/OCTEON-II_CN68XX. html.

[7] Tilera TILEPro64 Processor Product Brief. http: /www. tilera. com/sites/default/files/productbriefs/TILEPro64_Processor_PB019_v4. pdf.

[8] Bo Yuan, Hongbo Zhao, Chengchen Hu, Bin Liu, Jia Yu, Laxmi Bhuyan, Experience on Applying Push Model to Packet Processors in High Performance Routers, In Proceedings of Globecom, Miami, USA, 5-12 Dec. (2010).

DOI: 10.1109/glocom.2010.5683145

[9] Bin Liu, Bo Yuan, Huichen Dai, et al, Improving the Throughput and Delay Performance of Network Processors by Applying Push Model. In Proceeding of ACM/IEEE IWQoS, (2012).

DOI: 10.1109/iwqos.2012.6245973