Design of a Fourth-Order Sigma-Delta Modulator for Audio Application

Ming Yuan Ren; Tuo Li; Chang Chun Dong

doi:10.4028/www.scientific.net/AMM.380-384.3580

Paper Titles

Data Acquisition and Transmission Method of the Quality Traceability for Poultry Processing
p.3561

FCM Optimized with Differential Evolution for Image Segmentation
p.3566

Research on the Mining Technology of Multimedia Communication Data Flow Based on Computer Network
p.3570

Remote Access and Control System Based on Infrared Communication Technology
p.3575

Design of a Fourth-Order Sigma-Delta Modulator for Audio Application
p.3580

Research and Application of FPGA-Based Polling Strategy in Ad Hoc Network Data Acquisition System
p.3584

The Study in the Application of FFT in Vibroseis Data Harmonic Filtering
p.3589

Research of Recognition Algorithms by a Distance Feature Information Method on Digital Image
p.3595

The Distortion Analysis and Restraint of Dual-Frequency Modulation Signals
p.3599

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 380-384Design of a Fourth-Order Sigma-Delta Modulator for...

Design of a Fourth-Order Sigma-Delta Modulator for Audio Application

Abstract:

Based on requirements on high performance and high resolution of modulators, a fourth-order Sigma-Delta modulator for audio application is developed in this paper. The modulator is designed under the commercial 0.5μm CMOS process and the circuits are given simulations by Spectre. The sampling frequency of sigma-delta modulator is 11.264 MHz, and OSR is 256 within the 22 kHz signal bandwidth. Measure performance shows that Sigma-Delta modulator enables its maximum SNR to achieve 103.5dB, and the accuracy of Sigma-Delta modulator is up to 16 bit.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 380-384)

Pages:

3580-3583

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.380-384.3580

Citation:

Cite this paper

Online since:

August 2013

Authors:

Ming Yuan Ren, Tuo Li, Chang Chun Dong

Keywords:

CMOS, Modulator, Sigma-Delta

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] J. A. Cherry and W. M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion: Theory, Practice and Fundamental Performance Limits. New York, NY: Kluwer, (2002).

DOI: 10.22215/etd/1999-04133

Google Scholar

[2] S. R. Norsworthy, R. Schreier, and G. C. Temes, Eds., Delta-Sigma Data Converters: Theory, Design and Simulation. New York: IEEE Press, (1997).

DOI: 10.1109/9780470544358

Google Scholar

[3] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, E. Romani, A. Melodia, and V. Melini, A 14 b 20 mW 640 MHz CMOS CT Sigma-delta ADC with 20 MHz signal bandwidth and 12 b ENOB, in 2006 IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2006, p.131.

DOI: 10.1109/jssc.2006.884332

Google Scholar

[4] R. E. Radke, A. Eshraghi, and T. S. Fiez, A 14-bit current-mode Sigma-delta DAC based upon rotated data weighted averaging, IEEE J. Solid-State Circuits, vol. 35, no. 8, p.1074–1084, Aug. (2000).

DOI: 10.1109/4.859496

Google Scholar

[5] S. J. Huang and Y. Y. Lin, A 1. 2 V 2 MHz BW 0. 084 mm2 CT Sigma-delta ADC with 97. 7 dBc THD and 80 dB DR using low-latency DEM, in 2009 IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2009, p.172–173.

DOI: 10.1109/isscc.2009.4977363

Google Scholar

[6] Y. Tsividis, Continuous-time digital signal processing, Electron. Lett., vol. 39, no. 21, p.551–1552, Oct. (2003).

Google Scholar

[7] S. Naraghi, M. Courcy, and M. Flynn, A 9 b 14 μW 0. 06 mm PPM ADC in 90 nm digital CMOS, in 2009 IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2009, p.168–169.

DOI: 10.1109/jssc.2010.2050945

Google Scholar