A Low Power Design of SM4 Cipher Based on MUX S-Box Architecture

Yan Bo Niu; An Ping Jiang

doi:10.4028/www.scientific.net/AMM.411-414.125

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 411-414A Low Power Design of SM4 Cipher Based on MUX...

A Low Power Design of SM4 Cipher Based on MUX S-Box Architecture

Abstract:

SM4 is a 128-bit block cipher used in SOC and smart cards to ensure the safety of data transmission. In order to realize a low power implementation of the SM4 cipher block, some S-boxes were evaluated firstly and we proposed a new architecture of SM4 S-box called MUX S-box with a power consumption of 13.92W@10Mhz on SMIC 0.18m technology, Meanwhile, the implementation of SM4 cipher round based on the SM4 MUX S-box was completed and a low power consumption of 0.33mW @ 10 MHz on 0.18 m CMOS technology is achieved.

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Periodical:

Applied Mechanics and Materials (Volumes 411-414)

Pages:

125-130

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.411-414.125

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Online since:

September 2013

Authors:

Yan Bo Niu, An Ping Jiang

Keywords:

Multiplexer, S-Box, SM4-cipher, VLSI Design

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