A Kind of Logarithmic Function Hardware Encryptor and Decryptor

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This paper presents the realization of a kind of hardware encryptor and decryptor, which is based on Logarithmic Function principle. It shows how to design the encryption circuit and the decryption circuit by the sequential circuit. It had been designed in VHDL and simulated by Modelsim software, and then synthesized as well as realized on the FPGA chip EP2C5T144 by QuartusII software, last finished the test.

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2956-2959

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September 2013

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© 2013 Trans Tech Publications Ltd. All Rights Reserved

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[1] RUAN Wei-hua, The Realization of The Negative Logarithmic Function Based on FPGA, ICECC2011, 2011 International Conference on Electronics, Communications and Control[C], sep. 2011. 565-568.

DOI: 10.1109/icecc.2011.6067671

Google Scholar

[2] C. Layer, H-J. Pfleiderer, C. Heer, A Scalable Compact Architecture for the Computation of Integer Binary Logarithms Through Linear Approximation, Proc. IEEE ISCAS 2004[C], 2004. 421-424.

DOI: 10.1109/iscas.2004.1329298

Google Scholar

[3] D.K. Kostopoulos, An Algorithm for the Computation of Binary Logarithms, IEEE Transactions on Computers[J], Vol. 40, No. 11, Nov. 1991. 1267-1270.

DOI: 10.1109/12.102831

Google Scholar

[4] F.J. Taylor, R. Gill, J. Joseph, J. Radke, A 20 bit Logarithmic Number System Proce- ssor, IEEE Transactions on computer[J], Vol. 37, Issue 2, Feb. 1988. 190-200.

DOI: 10.1109/12.2148

Google Scholar

[5] K.H. Abed, R.E. Siferd, VLSI Implemen- tation of a Low-Power Antilogar- ithmic Converter, IEEE Transaction on Computers[J], Vol. 52, No. 9, Sep. 2003. 1221-1228.

DOI: 10.1109/tc.2003.1228517

Google Scholar

[6] K.H. Abed, R.E. Siferd, CMOS VLSI Implementation of a Low-Power Antilogar- ithmic Converter, IEEE Transaction on Computers[J], Vol. 52, No. 11, Nov. 2003. 1421-1433.

DOI: 10.1109/tc.2003.1244940

Google Scholar

[7] J.N. Mitchell, Computer Multiplication and Division Using Binary Logarithm, IRE Transactions on Electronics Computer[J], Vol. EC -11, Aug, 1962. 512-517.

DOI: 10.1109/tec.1962.5219391

Google Scholar