Synergy Micro-Electronics Technology with a High Linearity BiCMOS Sample-and-Hold Circuit

Jie Lin; Fei Yan Mu

doi:10.4028/www.scientific.net/AMM.473.50

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 473Synergy Micro-Electronics Technology with a High...

Synergy Micro-Electronics Technology with a High Linearity BiCMOS Sample-and-Hold Circuit

Abstract:

A high accuracy BiCMOS sample and hold (S/H) circuit employed in the front end of a12bit 10 MS/s Pipeline ADC is presented. To reduce the nonlinearity error cause by the sampling switch, a signal dependent clock bootstrapping system is introduced. It is implemented using 0.6 um BiCMOS process. An 88.77 dB spurious-free dynamic range (SFDR), and a -105.20 dB total harmonic distortion (THD) are obtained.

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Periodical:

Applied Mechanics and Materials (Volume 473)

Pages:

50-53

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.473.50

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Online since:

December 2013

Authors:

Jie Lin, Fei Yan Mu

Keywords:

Bootstrapped Switch, Gain-Boosting Operational Amplifier, Linearity, Sample-and-Hold, Synergy Micro-Electronics Technology

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