Design of MP3 Player Decoder Based on FPGA

Hang Xu

doi:10.4028/www.scientific.net/AMM.484-485.1029

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 484-485Design of MP3 Player Decoder Based on FPGA

Design of MP3 Player Decoder Based on FPGA

Abstract:

The paper takes a method of a low speed processer based on FPGA hardware accelerator SOC units to realize the MP3 player, and include some peripheral devices. The experimental results show that the system has implemented the basic functions of the MP3 player, having its own advantages on increasing the decoding speed and reducing the system consumption. The system is convenient to redesign for more function in the future. In conclusion, it has a wide application prospect.

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Periodical:

Applied Mechanics and Materials (Volumes 484-485)

Pages:

1029-1032

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.484-485.1029

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Online since:

January 2014

Authors:

Hang Xu

Keywords:

Decoder, FPGA, Huffman Decoding Principle, MP3 Player

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References

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