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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 536-537A Parallel Stereo Matching Algorithm Core for FPGA...

A Parallel Stereo Matching Algorithm Core for FPGA Modeled by DSP Builder

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Abstract:

This paper proposes a FPGA implementation to apply a stereo matching algorithm based on a kind of sparse census transform in a FPGA chip which can provide a high-definition dense disparity map in real-time. The parallel stereo matching algorithm core involves census transform, cost calculation and cost aggregation modules. The circuits of the algorithm core are modeled by the Matlab/Simulink-based tool box: DSP Builder. The system can process many different sizes of stereo pair images through a configuration interface. The maximum horizon resolution of stereo images is 2048.

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Advances in Mechatronics, Robotics and Automation II

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Periodical:

Applied Mechanics and Materials (Volumes 536-537)

Pages:

67-76

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.536-537.67

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Online since:

April 2014

Authors:

Xiang Zhang*, Zhang Wei Chen

Keywords:

Census Transform, Disparity, DSP Builder, FPGA, Stereo Matching

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© 2014 Trans Tech Publications Ltd. All Rights Reserved

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