Pattern Generation Research of BIST Based on Low Power

Yi Wang; Gui Juan Xu

doi:10.4028/www.scientific.net/AMM.543-547.701

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 543-547Pattern Generation Research of BIST Based on Low...

Pattern Generation Research of BIST Based on Low Power

Abstract:

In this paper, a new BIST structure is presented, which is generated by the LFSR modified. There is no redundant single input jump test incentive, all possible test vector combinations are covered, the testing power is reduced. Moreover, the testing time do not increase and fault-coverage rate won't be affected. Experiment results on the integrated circuit 74HC42 show that the switching activity reduction can be achieved up to 64% while achieving high fault coverage, especially suitable for BIST of Integrated circuits.

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Periodical:

Applied Mechanics and Materials (Volumes 543-547)

Pages:

701-704

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.543-547.701

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Cite this paper

Online since:

March 2014

Authors:

Yi Wang*, Gui Juan Xu

Keywords:

Build-In Self Test, Linear Feedback Shift Register, Low Power Dissipation, Random Single Input Change

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