An Implementation and Improvement of Fast Two-Dimensional Median Filtering

Gui Tang Wang; Rui Huang Wang; Feng Wang; Wen Juan  Liu

doi:10.4028/www.scientific.net/AMM.55-57.95

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 55-57An Implementation and Improvement of Fast...

An Implementation and Improvement of Fast Two-Dimensional Median Filtering

Abstract:

This paper discussed a conventional fast median filtering algorithm for FPGA implementation. An improved way -- Quasi-median filtering algorithm -- have been proposed to reduce the occupancy rate of FPGA resources on the premise of ensuring the result of median filtering. Through the detailed analysis and comparison of results of simulation and experiments, conclusions can be drawn that such improvements can achieve better filtering results, and can reduce FPGA resource utilization. It offers some value for the application of design which requires more FPGA resources.

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Periodical:

Applied Mechanics and Materials (Volumes 55-57)

Pages:

95-100

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.55-57.95

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Online since:

May 2011

Authors:

Gui Tang Wang, Rui Huang Wang, Feng Wang, Wen Juan Liu

Keywords:

Field-Programmable Gate Array (FPGA), Quasi-Median Filter, Verilog

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References

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