Design of Crossbar Arbiters in Tree-Based Routing Switches for On-Chip Networks

Abstract:

The mesh network is an important topology for on-chip networks since it provides great flexibility for the on-chip interconnection with diverse application requirements. We have proposed the tree-based routing architecture for on-chip networks called TRAIN, which achieves deadlock freedom and high-performance communication for on-chip networks. With TRAIN, a packet arriving in a switch can be adaptively routed to utilize a shortcut to reduce the distance to the destination switch efficiently. In this paper, we propose two arbitration schemes in a TRAIN switch and their arbiter designs: the sequential arbiter and the shortcut-first arbiter. The experimental results show that the shortcut-first arbiter achieves better performance than the sequential arbiter, while the former costs larger chip area. With the network size grows, the performance advantage is more pronounced for the shortcut-first arbiter.

• Periodical: Applied Mechanics and Materials (Volumes 556-562)
• Pages: 5609-5613
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.556-562.5609
• Online since: May 2014
• Authors: Hsin Chou Chi*, Hsi Che Tseng, Han Shien Weng
• Keywords: Crossbar Arbitration, On-Chip Networks, Switches, System-on-Chip Design, VLSI Design

References

[1] L. Benini and G. De Micheli, Networks on Chips: A New SoC Paradigm, IEEE Computer, Vol. 35, pp.70-78, Jan. (2002).

DOI: 10.1109/2.976921

[2] W.J. Dally and B. Towles, Route Packets, Not Wires: On-Chip Interconnection Networks, Proceedings of Design Automation Conference, pp.684-689, (2001).

DOI: 10.1109/dac.2001.935594

[3] J. Duato, Deadlock-Free Adaptive Routing Algorithms for Multicomputers: Evaluation of a New Algorithm, Proceedings of IEEE Symposium on Parallel and Distributed Processing, pp.840-847, Dec. (1991).

DOI: 10.1109/spdp.1991.218233

[4] H.C. Chi and C.T. Tang, A Deadlock-Free Routing Scheme for Interconnection Networks with Irregular Topologies, Proceedings of International Conference on Parallel and Distributed Systems, pp.88-95, Dec. (1997).

DOI: 10.1109/icpads.1997.652534

[5] H.C. Chi and W.J. Wu, Routing Tree Construction for Interconnection Networks with Irregular Topologies, Proceedings of Euromicro Conference on Parallel, Distributed and Network-Based Processing, pp.157-164, Feb. (2003).

DOI: 10.1109/empdp.2003.1183582

[6] R. Rojas-Cessa, E. Oki and H.J. Chao, On the Combined Input-Crosspoint Buffered Switch With Round-Robin Arbitration, IEEE Transactions on Communications, Vol. 53, pp.1945-1951, Nov. (2005).

DOI: 10.1109/tcomm.2005.858667

[7] J. Wang, Y. Li, Q. Peng and T. Tan, A Dynamic Priority Arbiter for Network-on-Chip, Proceedings of IEEE International Symposium on Industrial Embedded Systems, pp.253-256, Jul. (2009).

DOI: 10.1109/sies.2009.5196222

[8] L. Jain, B.M. Al-Hashimi, M.S. Gaur, V. Laxmi, A. Narayanan, NIRGAM: A Simulator for NoC Interconnect Routing and Application Modeling, Proceedings of Conference on Design, Automation and Test, Apr. (2007).