Using Verification Planner to Track the Verification Process

Article Preview

Abstract:

This paper will discuss how we integrated Verification Planner in our verification environment to generate better reports that can be used to track the progress of verification with the project manager. Using Verification Planner we were able to add coverage information to the Verification IP’s Excel based verification plans. We can then take advantage of Excel to generate better reports. Using a top-level plan, we were able to generate a summary page that could be shared with project manager, giving them the information they needed.

You might also be interested in these eBooks

Info:

Periodical:

Pages:

131-135

Citation:

Online since:

July 2014

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2014 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

* - Corresponding Author

[1] Janick Bergeron, Eduard Cerny, Alan Hunter and Andrew Nightingale. Verification Methodology Manual for SystemVerilog. 2005, Springer.

Google Scholar

[2] Verification Planner UserGuide. 2013, Synopsys.

Google Scholar

[3] DesignWare I2C Verification IP UVM User Manual. 2013, Synopsys.

Google Scholar