An Improved Low-Offset and Low-Power Design of Comparator for Flash ADC

Abstract:

This paper presents an offset-cancellation and low power cascaded comparator with new technique for flash Analog-to-Digital Converters. The improved structure cancels both input and output offset voltage by the feedback from outputs to common inputs. The total current consumption is reduced sharply for a clock circle with 1:2 dutyratio. The improved comparator is implemented in 0.35μm CMOS process. The Spectre simulation results show that the offset voltage of the improved structure is 3.14996mV with σ = 2.0347mV,and total current consumption is 17.59μA, while the offset voltage and total current consumption of the primary one is -5.649mV with σ = 14.254mV and 57.18μA respectively.

• Periodical: Applied Mechanics and Materials (Volume 598)
• Pages: 365-370
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.598.365
• Online since: July 2014
• Authors: Shuo Zhang*, Zong Min Wang, Liang Zhou
• Keywords: Comparator, Flash ADC, Low-Offset, Low-Power

References

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