Design and Implementation of FPGA-Based High-Performance Floating Point Arithmetic Unit

Xia Qing Tang; Xiang Liu; Jun Qiang Gao; Bo Lin

doi:10.4028/www.scientific.net/AMM.599-601.1465

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 599-601Design and Implementation of FPGA-Based...

Design and Implementation of FPGA-Based High-Performance Floating Point Arithmetic Unit

Abstract:

Since FPGA processing data, the presence of fixed-point processing accuracy is not high, and IP Core floating point unit and there are some problems in the use of design risk. Based on the improved floating point unit and program optimization algorithm is designed to achieve single-precision floating-point add / subtract, multiply, and divide operations operator. IP Core for floating-point unit design and FPGA development software provides comparative results: both the maximum clock frequency and latency basically unchanged, while the former occupies less hardware resources, to complete a plus / minus, multiply, divide computation time required for the former than the latter were reduced by 46%, 37% and 57%. The program is downloaded to the FPGA chip to get the same results with the simulation results verify the correctness and feasibility of the design.

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Periodical:

Applied Mechanics and Materials (Volumes 599-601)

Pages:

1465-1469

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.599-601.1465

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Online since:

August 2014

Authors:

Xia Qing Tang*, Xiang Liu, Jun Qiang Gao, Bo Lin

Keywords:

Floating-Point Operations, FPGA, Ip Core

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* - Corresponding Author

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