Front-End Design of High-Resolution Video Communication System Based on SoPC

Abstract:

Using high-resolution CCD chip and high-speed A/D converter chip, the design of the Video Communication System is given in this article, which successfully realizes the drive of the high-resolution area CCD and achieves the digital image signal. Based on the thought of SoPC’s (System on Programmable Chip) high integration, on the ALTERA company's DE2 platform, FPGA is used to achieve the driving timing of CCD, Silicon delay lines are used to properly align the pixel rate CCD clock signals with respect to one another, and the push-pull transistor circuits are designed to translate TTL level driving clock signal to the voltage levels required by the CCD. The system demonstrates some application values by analysis.

• Periodical: Applied Mechanics and Materials (Volumes 608-609)
• Pages: 670-673
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.608-609.670
• Online since: October 2014
• Authors: Qi Zhu*
• Keywords: A/D Conversion, Area CCD Driving, Charge Coupled Devices (CCD), System on Programmable Chip (SOPC), Video Capture System

References

[1] Zhou Ligong, Basic course of SoPC embedded system [M], Beijing: Beijing University of Aeronautics and Astronautics Press, (2006).

[2] KODAK KAF-8300 IMAGE SENSOR Handbook. www. kodak. com/go/imagers, (2008).

[3] Mibenheye (Japan), Basis and application of CCD/CMOS image sensor, Beijing: Science Press, (2005).

[4] KODAK AREA ARRAY CCD TIMING GENERATOR BOARD USERS MANUAL. http: /www. kodak. com/go/imagers. (2003).

[5] Altera Corporation. QuartusII Verision 6. 0 Handbook, (2006).

[6] Altera Corporation. Nios II Software Developer's Handbook, (2006).

[7] DS1021 Programmable 8 bit Silicon Delay Line Datasheet. http: /www. maxim-ic. com. cn. (2003).

[8] DS1040 Programmable One-Shot Pulse Generator Datasheet. http: /www. maxim-ic. com. cn. (2003).