Thermal Mechanics Based Energy Efficient FIR Filter for Digital Signal Processing

Abstract:

Thermal mechanism cover the mechanics of Hit Sink, Airflow mechanics, and Ambient Temperature Mechanism to reduce junction temperature in design of Finite Duration Impulse Response (FIR) Filter. In this work, we are implementing FIR Filter on 28nm FPGA. After implementation of FIR Filter, we analyze the effect of in-built mechanism of Air Flow Controller and their produced Airflow on the junction temperature of FPGA. The mechanism of Ambient Temperature controller also play significant role in leakage power dissipation as well as junction temperature of FPGA. Finally, the mechanical structure of Hit Sink is considered for control of junction temperature of FPGA. There is 73.38% reduction in Leakage Power on 55 C ambient temperature when we increase airflow from 250 LFM to 500 LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 78.31% reduction in leakage power. There is 37.68% reduction in junction temperature of FPGA when we increase airflow from 250LFM to 500LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 41.76 % reduction in junction temperature on 45C ambient temperature. There is no effect of airflow on clock power. Whereas there is significant reduction in Logic Power, Signal Power, DSPs Power and IOs Power with change in Airflow.

• Periodical: Applied Mechanics and Materials (Volume 612)
• Pages: 65-70
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.612.65
• Online since: August 2014
• Authors: Bishwajeet Pandey*, Tanesh Kumar, Teerath Das, S.M.M. Islam, Jagdish Kumar
• Keywords: Fibonacci Generator, FPGA, HSTL, I/O Standard, I/Os Power, Low Power, VLSI

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