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Design of a 0.7~2.6GHz Wideband Power Amplifier in 0.18-μm CMOS Process
Abstract:
A power amplifier (PA) for multi-mode multi-standard transceiver which is implemented in a TSMC 0.18μm process is presented. The proposed PA uses matching compensation, lossy matching network and negative feedback technique to improve bandwidth. To achieve the linearity performance, the two-stage PA operates in Class-A regime. Simulation results show that the power amplifier achieves maximum output power of more than 24dBm in 0.7~2.6GHz. The output P1dB of the PA is larger than 22dBm. The simulated power gain is more than 27dB. The S11 is less than-10dB and the S22 is under-5dB.
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543-547
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Online since:
August 2014
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© 2014 Trans Tech Publications Ltd. All Rights Reserved
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