Reliability Oriented Selective Triple Modular Redundancy for SRAM-Based FPGAs

Mei Song Zheng; Zi Long Wang; Ji Tu; Jun Ye Wang; Li Jian Li

doi:10.4028/www.scientific.net/AMM.713-715.1127

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 713-715Reliability Oriented Selective Triple Modular...

Reliability Oriented Selective Triple Modular Redundancy for SRAM-Based FPGAs

Abstract:

This paper presents an improved approach to Triple Modular Redundancy (TMR) which concerns don’ t care bits of LUT configuration bits and hence classifies the set of LUTs into SEU-sensitive and SEU-insensitive. Unlike the full TMR approach, the improved approach only triplicates SEU-sensitive LUTs and can greatly reduces the area overhead while maintaining the circuit reliability. The proposed approach is thoroughly tested on the MCNC’91 benchmarks. Compare with the full TMR method the proposed scheme can reduce the area overhead by 26.6% on average, at the same time the circuit reliability only reduced by 9.1 %. The improved approach can also increase mean time between failures (MTBF) by an average of six times more than the original circuit.

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Periodical:

Applied Mechanics and Materials (Volumes 713-715)

Pages:

1127-1131

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.713-715.1127

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Online since:

January 2015

Authors:

Mei Song Zheng*, Zi Long Wang, Ji Tu, Jun Ye Wang, Li Jian Li

Keywords:

Don’T Care Bits (DC), Field Programmable Gate Array (FPGA), Single Event Upset (SEU), Triple Modular Redundancy (TMR), Windowing

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