Design and Implementation of an Encryption/Decryption System Based on FPGA

Xiao Cong Ma; Guang Hui Cai; Hong Chao Sun; Hong Ye Li

doi:10.4028/www.scientific.net/AMR.1022.368

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 1022Design and Implementation of an...

Design and Implementation of an Encryption/Decryption System Based on FPGA

Abstract:

This paper designs an encryption and decryption system based on the FPGA. The system uses AES algorithm to encrypt and decrypt data. A pipeline IP core is designed with the reconfigurable technology complying with the Avalon bus interface specification. The IP core is applied to be a custom component on Nios II architecture so that the encryption and decryption processes through hardware can be controlled by software. Finally, the program is downloaded to the Altera DE2 development board and completes the testing of encryption and decryption processes. The system can be widely implemented in the field of data security.

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Periodical:

Advanced Materials Research (Volume 1022)

Pages:

368-371

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.1022.368

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Cite this paper

Online since:

August 2014

Authors:

Xiao Cong Ma*, Guang Hui Cai, Hong Chao Sun, Hong Ye Li

Keywords:

AES Algorithm, IP Core, Nios II, Pipeline

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* - Corresponding Author

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