[1]
Irturk A, Benson B, Mirzaei S, et al. An FPGA design space exploration tool for matrix inversion architectures[C]/Application Specific Processors, 2008. SASP 2008. Symposium on. IEEE, 2008: 42-47.
DOI: 10.1109/sasp.2008.4570784
Google Scholar
[2]
Irturk A, Mirzaei S, Kastner R. FPGA implementation of adaptive weight calculation core using QRD-RLS algorithm[M]. Department of Computer Science and Engineering, University of California, San Diego, (2009).
Google Scholar
[3]
Teitelbaum K. A flexible processor for a digital adaptive array radar [C]/Radar Conference, 1991., Proceedings of the 1991 IEEE National. IEEE, 1991: 103-107.
DOI: 10.1109/nrc.1991.114739
Google Scholar
[4]
Zeng T. High-speed parallel DSP DBF system and algorithm research [D]. Chengdu: University of Electronic Science and Technology of China Signal and Information Processing, 1998. (in Chinese).
Google Scholar
[5]
Maltsev A, Pestretsov V, Maslennikov R, et al. Triangular systolic array with reduced latency for QR-decomposition of complex matrices [C]/ISCAS. 2006, 6: 21-24.
DOI: 10.1109/iscas.2006.1692603
Google Scholar
[6]
Z. Liu, K. Dickson, and J. V. McCanny. Application-specific instruction set processor for SoC implementation of modern signal processing algorithms [J]. IEEE Transactions on Circuits Syst. I, Reg. Papers, vol. 52, no. 4, p.755–765, Apr. (2005).
DOI: 10.1109/tcsi.2005.844109
Google Scholar
[7]
C K Singh, S H Prasad, P T Balsara. VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition[C]/VLSI Design. 2007: 836-841.
DOI: 10.1109/vlsid.2007.177
Google Scholar
[8]
C. K. Singh, S. H. Prasad, and P. T. Balsara. A fixed-point implementation for QR decomposition [J]. in Proc. IEEE Dallas Workshop Des. Appl. Integr. Softw., Oct. 2006, p.75–78.
DOI: 10.1109/dcas.2006.321037
Google Scholar
[9]
Hu B X, Dong W, Yu Q. A recursive QRD-LS algorithm based on householder transformation [J]. Signal Processing, 2006, 22(1): 53-56. (in Chinese).
Google Scholar
[10]
Volder J E. The CORDIC trigonometric computing technique [J]. IRE Trans. , 1959, EC-8(3).
DOI: 10.1109/tec.1959.5222693
Google Scholar
[11]
RADER C M. VLSI Systolic arrays for adaptive nulling. IEEE Signal Processing Magazine, 1996. 29-49.
DOI: 10.1109/79.526897
Google Scholar
[12]
Chang R C H, Lin C H, Lin K H, et al. Iterative decomposition architecture using the modified Gram–Schmidt algorithm for MIMO systems[J]. Circuits and Systems I: Regular Papers, IEEE Transactions on, 2010, 57(5): 1095-1102.
DOI: 10.1109/tcsi.2010.2047744
Google Scholar