Design of Digital Pulse Compression System Based on FPGA

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Abstract:

Pulse compression technology is one of the key technologies in the field of modern radar signal processing, can effectively solve the contradiction between action distance and resolution. In this paper, a radar digital pulse compression system is designed and implemented based on FPGA with linear frequency modulated signal. The digital pulse compression module is designed using FFT IP core which can be reused in different periods of DPC, respectively performing FFT and IFFT calculation, so that the hardware consumption is saved significantly. Therefore, compared with other systems, the system designed in this paper has the characters of fast processing speed, high degree of modularity, real-time processing and short development cycle.

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Periodical:

Advanced Materials Research (Volumes 1049-1050)

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1718-1721

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Online since:

October 2014

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© 2014 Trans Tech Publications Ltd. All Rights Reserved

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[1] R Radhouane, P Liu, C Modlin, Minimizing the Memory Requirement for Continuous Flow FFT Implementation: Continuous Flow Mixed Mode FFT(CMFF - FFT) 1ISCAS 2000, IEEE, May 28 -31.

DOI: 10.1109/iscas.2000.857040

Google Scholar

[2] S-F Hsiao, M-R Jiang. Efficient Synthesiser for Generation of Fast Parallel Multiplier[J]. Computers and Digital Technology , IEEE Proceedings2 , Jan. 2000 , 147(1) : 49-52.

Google Scholar

[3] Mori, M Nagamatsu. A 10 ns 5454-b Parallel St ructure Full Array Multiplier with 0. 5 CMOS Technology[J] . IEEE J of Solid-State Circuits , 1991 , 26 (4) : 600-606.

DOI: 10.1109/4.75061

Google Scholar