Architecture-Specific Mapping Tool for SOI-Based FPGA

Abstract:

This paper addresses several key issues in the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process, with particular emphasis on FPGA architecture interrelated mapping step and packing method for CAD tool. Considering the routability and testability of the FPGA and the CAD tool, the algorithm combines the FPGA structure with the object netlist, mapping the basic elements into basic building blocks in order to reduce the resource usage. The result is proven in extensive test circuits used in our FPGA design.

• Periodical: Advanced Materials Research (Volume 159)
• Pages: 438-443
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.159.438
• Online since: December 2010
• Authors: Qian Li Zhang, Fang Yu, Yan Li, Ming Li, Yan Zhao, Liang Chen
• Keywords: CAD Tool, Mapping, Packing, Routibility, SOI-Based FPGA, Testability

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